參數(shù)資料
型號(hào): SC16IS760IBS,151
廠商: NXP Semiconductors
文件頁(yè)數(shù): 14/16頁(yè)
文件大小: 0K
描述: IC UART I2C/SPI 24-HVQFN
產(chǎn)品培訓(xùn)模塊: Bridge Solutions
Stand-Alone UARTs
I²C Bus Fundamentals
特色產(chǎn)品: NXP - I2C Interface
標(biāo)準(zhǔn)包裝: 490
特點(diǎn): 低電流
通道數(shù): 1,UART
FIFO's: 64 字節(jié)
規(guī)程: RS232,RS485
電源電壓: 2.5V, 3.3V
帶自動(dòng)流量控制功能:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
安裝類(lèi)型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 24-HVQFN(4x4)
包裝: 托盤(pán)
產(chǎn)品目錄頁(yè)面: 828 (CN2011-ZH PDF)
配用: 568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
其它名稱(chēng): 568-2238
935279279151
SC16IS760IBS-S
2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FIN224C Rev. 1.0.9
7
SerD
es
FIN
224C
24-
B
it
Low-
P
ower
Serializer/D
eserializer
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
tTPLLS0
Phase Lock Loop Stabilization Time
200
s
tTPLLD0
PLL Disable Time Loss of Clock
30
s
AC Deserializer, DIRI = 0 Specifications
tSKEW_DS-
CKS
Allowed DS-CKS Input Signal Skew
-150
150
ps
tRCOH
CKP Out Low Time
CKREF = STROBE, a = (1/f)/13
13a-3
13a+3
ns
tRCOH
CKP Out High Time
13a-3
13a+13
ns
tPDV
Data Valid to CKP Low
8a-6
8a+1
ns
tROLH
Output Rise Time (20% to 80%)
18
ns
tROLH
Output Fall Time (20% to 80%)
18
ns
AC Enable and Disable Timing
tPLZ(HZ)
Deserializer Disable Time
25
ns
tPZL(ZH)
Deserializer Enable Time
2
s
tPLZ(HZ)
Serializer Disable Time
25
ns
tPZL(ZH)
Serializer Enable Time
65
ns
Notes:
2.
Skew is measured from either the rising or falling edge of CKSO clock to the rising or falling edge of DSO. Signals are
edge aligned. Both outputs should have identical load condtions for this test to be valid.
3.
If CKREF is not equal to STROBE for the serializer, the CKP signal does not maintain a 50% duty cycle. The low time of
CKP remains 13 bit times.
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