參數資料
型號: SC16IS752IBS,128
廠商: NXP Semiconductors
文件頁數: 29/60頁
文件大?。?/td> 0K
描述: IC UART DUAL I2C/SPI 32-HVQFN
標準包裝: 1,500
特點: 低電流
通道數: 2,DUART
FIFO's: 64 字節(jié)
規(guī)程: RS232,RS485
電源電壓: 2.5V, 3.3V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調制解調器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤
供應商設備封裝: 32-HVQFN(5x5)
包裝: 帶卷 (TR)
配用: 568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
其它名稱: 935279288128
SC16IS752IBS-F
SC16IS752IBS-F-ND
SC16IS752_SC16IS762
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 9 — 22 March 2012
35 of 60
NXP Semiconductors
SC16IS752; SC16IS762
Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
10. I2C-bus operation
The two lines of the I2C-bus are a serial data line (SDA) and a serial clock line (SCL). Both
lines are connected to a positive supply via a pull-up resistor, and remain HIGH when the
bus is not busy. Each device is recognized by a unique address whether it is a
microcomputer, LCD driver, memory or keyboard interface and can operate as either a
transmitter or receiver, depending on the function of the device. A device generating a
message or data is a transmitter, and a device receiving the message or data is a
receiver. Obviously, a passive function like an LCD driver could only be a receiver, while a
microcontroller or a memory can both transmit and receive data.
10.1 Data transfers
One data bit is transferred during each clock pulse (see Figure 12). The data on the SDA
line must remain stable during the HIGH period of the clock pulse in order to be valid.
Changes in the data line at this time will be interpreted as control signals. A HIGH-to-LOW
transition of the data line (SDA) while the clock signal (SCL) is HIGH indicates a START
condition, and a LOW-to-HIGH transition of the SDA while SCL is HIGH defines a STOP
condition (see Figure 13). The bus is considered to be busy after the START condition
and free again at a certain time interval after the STOP condition. The START and STOP
conditions are always generated by the master.
The number of data bytes transferred between the START and STOP condition from
transmitter to receiver is not limited. Each byte, which must be eight bits long, is
transferred serially with the most significant bit first, and is followed by an acknowledge bit
(see Figure 14). The clock pulse related to the acknowledge bit is generated by the
master. The device that acknowledges has to pull down the SDA line during the
acknowledge clock pulse, while the transmitting device releases this pulse (see
Fig 12. Bit transfer on the I2C-bus
Fig 13. START and STOP conditions
mba607
data line
stable;
data valid
change
of data
allowed
SDA
SCL
mba608
SDA
SCL
P
STOP condition
S
START condition
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