參數(shù)資料
型號: SC16C852VIET
廠商: NXP Semiconductors N.V.
元件分類: 收發(fā)器
英文描述: 1.8 V dual UART, 5 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA) and XScale VLIO bus interface
封裝: SC16C852VIET<SOT912-1 (TFBGA36)|<<http://www.nxp.com/packages/SOT912-1.html<1<Always Pb-free,;SC16C852VIET<SOT912-1 (TFBGA36)|<<http://www.nxp.com/packages/SOT912-1.html&
文件頁數(shù): 33/55頁
文件大小: 390K
代理商: SC16C852VIET
SC16C852V
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 21 January 2011
33 of 55
NXP Semiconductors
SC16C852V
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
7.14 Enhanced Feature Register (EFR)
Enhanced features are enabled or disabled using this register.
Bit 0 through bit 4 provide single or dual character software flow control selection. When
the Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double 8-bit words are
concatenated into two sequential numbers.
Table 25.
Bit
7
[1]
Enhanced function control bits: IER[7:4], ISR[5:4], FCR[5:4] and MCR[7:5].
Table 26.
Cont-3
0
1
0
Enhanced Feature Register bits description
Symbol
Description
EFR[7]
Automatic CTS flow control.
logic 0 = automatic CTS flow control is disabled (normal default condition)
logic 1 = enable automatic CTS flow control. Transmission will stop when
CTS goes to a logical 1. Transmission will resume when the CTS signal
returns to a logical 0.
EFR[6]
Automatic RTS flow control. Automatic RTS may be used for hardware flow
control by enabling EFR[6]. When Auto-RTS is selected, an interrupt will be
generated when the receive FIFO is filled to the programmed trigger level and
RTS will go to a logic 1 at the next trigger level. RTS will return to a logic 0 when
data is unloaded below the next lower trigger level (programmed trigger level 1).
The state of this register bit changes with the status of the hardware flow
control. RTS functions normally when hardware flow control is disabled.
logic 0 = automatic RTS flow control is disabled (normal default condition)
logic 1 = enable automatic RTS flow control
EFR[5]
Special character detect.
logic 0 = special character detect disabled (normal default condition)
logic 1 = special character detect enabled. The SC16C852V compares each
incoming receive character with Xoff2 data. If a match exists, the received
data will be transferred to FIFO and ISR[4] will be set to indicate detection of
special character. Bit-0 in the X-registers corresponds with the LSB bit for the
receive character. When this feature is enabled, the normal software flow
control must be disabled (EFR[3:0] must be set to a logic 0).
EFR[4]
Enhanced function control bit. The content of IER[7:4], ISR[5:4], FCR[5:4], and
MCR[7:5] can be modified and latched. After modifying any bits in the enhanced
registers, EFR[4] can be set to a logic 0 to latch the new values. This feature
prevents existing software from altering or overwriting the SC16C852V
enhanced functions.
logic 0 = disable/latch enhanced features
[1]
logic 1 = enables the enhanced functions
[1]
. When this bit is set to a logic 1,
all enhanced features of the SC16C852V are enabled and user settings
stored during a reset will be restored.
EFR[3:0]
Cont-3:0 Tx, Rx control. Logic 0 or cleared is the default condition.
Combinations of software flow control can be selected by programming these
bits. See
Table 26
.
6
5
4
3:0
Software flow control functions
[1]
Cont-2
Cont-1
0
X
0
X
1
X
Cont-0
X
X
X
TX, RX software flow controls
No transmit flow control
Transmit Xon1/Xoff1
Transmit Xon2/Xoff2
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SC16C852VIET,515 制造商:NXP Semiconductors 功能描述: