參數(shù)資料
型號(hào): SC16C852LIET
廠商: NXP Semiconductors N.V.
元件分類: 收發(fā)器
英文描述: 1.8 V dual UART, 5 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA) and 16 mode or 68 mode bus interface
封裝: SC16C852LIB<SOT313-2 (LQFP48)|<<http://www.nxp.com/packages/SOT313-2.html<1<Always Pb-free,;SC16C852LIB<SOT313-2 (LQFP48)|<<http://www.nxp.com/packages/SOT313-2.html<1
文件頁數(shù): 28/64頁
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代理商: SC16C852LIET
SC16C852L
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 1 February 2011
28 of 64
NXP Semiconductors
SC16C852L
1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder
7.3 FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger
levels, and select the DMA mode.
7.3.1
DMA mode
7.3.1.1
Mode 0 (FCR bit 3 = 0)
In this mode, Transmit Ready (TXRDY) will go to a logic 0 whenever the FIFO (THR, if
FIFO is not enabled) is empty. Receive Ready (RXRDY) will go to a logic 0 whenever the
Receive Holding Register (RHR) is loaded with a character.
7.3.1.2
Mode 1 (FCR bit 3 = 1)
In this mode, the Transmit Ready (TXRDY) is set when the transmit FIFO is below the
programmed trigger level. The Receive Ready (RXRDY) is set when the receive FIFO fills
to the programmed trigger level. However, the FIFO continues to fill regardless of the
programmed level until the FIFO is full. RXRDY remains a logic 0 as long as the FIFO fill
level is above the programmed trigger level.
7.3.2
FIFO mode
Table 12.
Bit
7:6
FIFO Control Register bits description
Symbol
Description
FCR[7:6]
Receive trigger level in 32-byte FIFO mode
[1]
.
These bits are used to set the trigger levels for receive FIFO interrupt and
flow control. The SC16C852L will issue a receive ready interrupt when the
number of characters in the receive FIFO reaches the selected trigger level.
Refer to
Table 13
.
FCR[5:4]
Transmit trigger level in 32-byte FIFO mode
[2]
.
These bits are used to set the trigger level for the transmit FIFO interrupt and
flow control. The SC16C852L will issue a transmit empty interrupt when the
number of characters in FIFO drops below the selected trigger level. Refer to
Table 14
.
FCR[3]
DMA mode select.
logic 0 = set DMA mode ‘0’ (normal default condition)
logic 1 = set DMA mode ‘1’
Transmit operation in mode ‘0’:
When the SC16C852L is in the non-FIFO
mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode (FIFOs
enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there are no
characters in the transmit FIFO, the TXRDYA/TXRDYB pin will be a logic 0.
Once active, the TXRDYA/TXRDYB pin will go to a logic 1 after the first
character is loaded into the transmit holding register.
Receive operation in mode ‘0’:
When the SC16C852L is in non-FIFO
mode, or in the FIFO mode (FCR[0] = logic 1; FCR[3] = logic 0) and there is
at least one character in the receive FIFO, the RXRDYA/RXRDYB pin will be
a logic 0. Once active, the RXRDYA/RXRDYB pin will go to a logic 1 when
there are no more characters in the receiver.
5:4
3
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