參數(shù)資料
型號: SC16C850IBS,157
廠商: NXP Semiconductors
文件頁數(shù): 54/55頁
文件大小: 0K
描述: IC UART SGL W/FIFO 32HVQFN
標(biāo)準(zhǔn)包裝: 2,450
特點(diǎn): 可編程
通道數(shù): 1,UART
FIFO's: 128 字節(jié)
規(guī)程: RS485
電源電壓: 2.5 V ~ 3.3 V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-HVQFN(5x5)
包裝: 托盤
SC16C850
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 11 November 2010
8 of 55
NXP Semiconductors
SC16C850
2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder
[1]
HVQFN32 package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must be connected to supply
ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be
soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias
need to be incorporated in the PCB in the thermal pad region.
RTS
D2
21
O
Request to Send (active LOW). A logic 0 on the RTS pin indicates the
transmitter has data ready and waiting to send. Writing a logic 1 in the modem
control register MCR[1] will set this pin to a logic 0, indicating data is available.
After a reset this pin will be set to a logic 1.
RX
C6
6
I
UART receive data. The RX signal will be a logic 1 during reset, idle (no
data), or when not receiving data. During the local loopback mode, the RX
input pin is disabled and TX data is connected to the UART RX input,
internally.
TX
C5
7
O
UART transmit data. The TX signal will be a logic 1 during reset, idle (no
data), or when the transmitter is disabled. During the local loopback mode, the
TX output pin is disabled and TX data is internally connected to the UART RX
input.
VDD
A1, D4
28
I
Power supply input.
VSS
C2, C4
I
Signal and power ground.
XTAL1
A6
10
I
Crystal or external clock input. Functions as a crystal input or as an external
clock input. A crystal can be connected between this pin and XTAL2 to form an
internal oscillator circuit. Alternatively, an external clock can be connected to
this pin to provide custom data rates (see Section 6.9 “Programmable baud
XTAL2
A5
11
O
Output of the crystal oscillator or buffered clock. (See also XTAL1.)
Crystal oscillator output or buffered clock output. Should be left open if an
external clock is connected to XTAL1.
Table 2.
Pin description …continued
Symbol
Pin
Type
Description
TFBGA36
HVQFN32
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