參數(shù)資料
型號: SC16C754
廠商: NXP Semiconductors N.V.
英文描述: Quad UART with 64-byte FIFO
中文描述: 四UART的64字節(jié)FIFO
文件頁數(shù): 14/49頁
文件大?。?/td> 622K
代理商: SC16C754
Philips Semiconductors
SC16C754
Quad UART with 64-byte FIFO
Product data
Rev. 04 — 19 June 2003
14 of 49
9397 750 11618
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
6.5 Interrupts
The SC16C754 has interrupt generation and prioritization (six prioritized levels of
interrupts) capability. The interrupt enable register (IER) enables each of the six types
of interrupts and the INT signal in response to an interrupt generation. The IER can
also disable the interrupt system by clearing bits 0-3, 5-7. When an interrupt is
generated, the IIR indicates that an interrupt is pending and provides the type of
interrupt through IIR[5;0].
Table 6
summarizes the interrupt control functions.
It is important to note that for the framing error, parity error, and break conditions,
LSR[7] generates the interrupt. LSR[7] is set when there is an error anywhere in the
RX FIFO, and is cleared only when there are no more errors remaining in the FIFO.
LSR[4:2] always represent the error status for the received character at the top of the
RX FIFO. Reading the RX FIFO updates LSR[4:2] to the appropriate status for the
new character at the top of the FIFO. If the RX FIFO is empty, then LSR[4:2] are all
zeros.
For the Xoff interrupt, if an Xoff flow character detection caused the interrupt, the
interrupt is cleared by an Xon flow character detection. If a special character
detection caused the interrupt, the interrupt is cleared by a read of the LSR.
Table 6:
IIR[5:0]
Interrupt control functions
Priority
level
None
none
1
receiver line status
Interrupt type
Interrupt source
Interrupt reset method
000001
000110
none
OE, FE, PE, or BI errors occur in
characters in the RX FIFO
none
FE, PE, BI: all erroneous
characters are read from the
RX FIFO.
OE: read LSR
read RHR
read RHR
001100
000100
2
2
RX time-out
RHR interrupt
stale data in RX FIFO
DRDY (data ready)
(FIFO disable)
RX FIFO above trigger level
(FIFO enable)
TFE (THR empty)
(FIFO disable)
TX FIFO passes above trigger level
(FIFO enable)
MSR[3:0] = 0
receive Xoff character(s)/special
character
RTS pin or CTS pin change state from
active (LOW) to inactive (HIGH)
000010
3
THR interrupt
read IIR
or
a write to the THR
000000
010000
4
5
modem status
Xoff interrupt
read MSR
receive Xon character(s)/Read of
IIR
read IIR
100000
6
CTS, RTS
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SC16C754BIA68,512 功能描述:UART 接口集成電路 16CB 2.5V-5V 4CH RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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