參數(shù)資料
型號(hào): SC16C750BIBS,128
廠商: NXP Semiconductors
文件頁(yè)數(shù): 41/44頁(yè)
文件大?。?/td> 0K
描述: IC UART 64BYTE 32HVQFN
標(biāo)準(zhǔn)包裝: 6,000
通道數(shù): 1,UART
FIFO's: 64 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動(dòng)流量控制功能:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-HVQFN(5x5)
包裝: 帶卷 (TR)
其它名稱: 935276388128
SC16C750BIBS-F
SC16C750BIBS-F-ND
SC16C750B_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 17 October 2008
6 of 44
NXP Semiconductors
SC16C750B
5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs
CTS
40
33
25
I
Clear to send. CTS is a modem status signal. Its condition can be
checked by reading bit 4 (CTS) of the Modem Status Register
(MSR). MSR[3] (
CTS) indicates that CTS has changed states
since the last read from the MSR. If the modem status interrupt is
enabled when CTS changes levels and the auto-CTS mode is not
enabled, an interrupt is generated. CTS is also used in the
auto-CTS mode to control the transmitter.
D7 to D0
9, 8, 7,
6, 5, 4,
3, 2
52, 51, 50,
48, 46, 45,
43, 42
3, 2, 1, 32,
31, 30,
29, 28
I/O
Data bus. Eight data lines with 3-state outputs provide a
bidirectional path for data, control and status information between
the UART and the CPU.
DCD
42
36
-
I
Data carrier detect. DCD is a modem status signal. Its condition
can be checked by reading bit 7 (DCD) of the Modem Status
Register (MSR). MSR[3] (
DCD) indicates that DCD has changed
states since the last read from the MSR. If the modem status
interrupt is enabled when DCD changes levels, an interrupt is
generated.
DDIS
26
12
-
O
Driver disable. DDIS is active (LOW) when the CPU is reading
data. When inactive (HIGH), DDIS can disable an external
transceiver.
DSR
41
35
26
I
Data set ready. DSR is a modem status signal. Its condition can be
checked by reading bit 5 (DSR) of the Modem Status Register. Bit 1
(DDSR) of the MSR indicates DSR has changed levels since the
last read from the MSR. If the modem status interrupt is enabled
when DSR changes levels, an interrupt is generated.
DTR
37
28
22
O
Data terminal ready. When active (LOW), DTR informs a modem
or data set that the UART is ready to establish communication. DTR
is placed in the active level by setting the DTR bit of the Modem
Control Register. DTR is placed in the inactive level either as a
result of a Master Reset, during Loopback mode operation, or
clearing the DTR bit.
INT
33
23
20
O
Interrupt. When active (HIGH), INT informs the CPU that the UART
has an interrupt to be serviced. Four conditions that cause an
interrupt to be issued are: a receiver error, received data that is
available or timed out (FIFO mode only), an empty transmitter
holding register or an enabled modem status interrupt. INT is reset
(deactivated) either when the interrupt is serviced or as a result of a
Master Reset.
n.c.
34
3, 5, 7, 11,
14, 16, 19,
22, 24, 27,
29, 31, 34,
37, 39, 41,
44, 47, 49,
53, 56, 57,
60, 63
12
-
not connected
OUT1,
OUT2
38, 35
30, 25
-
O
Outputs 1 and 2. These are user-designated output terminals that
are set to the active (LOW) level by setting respective Modem
Control Register (MCR) bits (OUT1 and OUT2). OUT1 and OUT2
are set to inactive the (HIGH) level as a result of Master Reset,
during Loopback mode operations, or by clearing bit 2 (OUT1) or
bit 3 (OUT2) of the MCR.
OUT
-
23
O
Table 2.
Pin description …continued
Symbol
Pin
Type
Description
PLCC44 LQFP64
HVQFN32
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