參數(shù)資料
型號: SC16C654BIB64
廠商: NXP Semiconductors N.V.
元件分類: 收發(fā)器
英文描述: 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit-s (max.), with 64-byte FIFOs and infrared (IrDA) encoder-decoder
封裝: SC16C654BIA68<SOT188-2 (PLCC68)|<<http://www.nxp.com/packages/SOT188-2.html<1<Always Pb-free,;SC16C654BIA68<SOT188-2 (PLCC68)|<<http://www.nxp.com/packages/SOT188-2.html&
文件頁數(shù): 29/58頁
文件大小: 302K
代理商: SC16C654BIB64
9397 750 14965
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 20 June 2005
29 of 58
Philips Semiconductors
SC16C654B/654DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
7.4 Interrupt Status Register (ISR)
The SC16C654B/654DB provides six levels of prioritized interrupts to minimize external
software interaction. The Interrupt Status Register (ISR) provides the user with six
interrupt status bits. Performing a read cycle on the ISR will provide the user with the
highest pending interrupt level to be serviced. No other interrupts are acknowledged until
the pending interrupt is serviced. Whenever the interrupt status register is read, the
interrupt status is cleared. However, it should be noted that only the current pending
interrupt is cleared by the read. A lower level interrupt may be seen after re-reading the
interrupt status bits.
Table 13 “Interrupt source”
shows the data values (bits 0:5) for the six
prioritized interrupt levels and the interrupt sources associated with each of these interrupt
levels.
Table 13:
Priority
level
1
Interrupt source
ISR[5]
ISR[4]
ISR[3]
ISR[2]
ISR[1]
ISR[0]
Source of the interrupt
0
0
0
1
1
0
LSR (Receiver Line Status
Register)
RXRDY (Receive Data
Ready)
RXRDY (Receive Data
time-out)
TXRDY(TransmitterHolding
Register Empty)
MSR (Modem Status
Register)
RXRDY (Received Xoff
signal)/Special character
CTS, RTS change of state
2
0
0
0
1
0
0
2
0
0
1
1
0
0
3
0
0
0
0
1
0
4
0
0
0
0
0
0
5
0
1
0
0
0
0
6
1
0
0
0
0
0
Table 14:
Bit
7:6
Interrupt Status Register bits description
Symbol
Description
ISR[7:6]
FIFOs enabled. These bits are set to a logic 0 when the FIFO is not
being used. They are set to a logic 1 when the FIFOs are enabled.
logic 0 or cleared = default condition
ISR[5:4]
INT priority bits 4:3. These bits are enabled when EFR[4] is set to a
logic 1. ISR[4] indicates that matching Xoff character(s) have been
detected. ISR[5] indicates that CTS, RTS have been generated. Note
that once set to a logic 1, the ISR[4] bit will stay a logic 1 until Xon
character(s) are received.
logic 0 or cleared = default condition
ISR[3:1]
INT priority bits 2:0. These bits indicate the source for a pending
interrupt at interrupt priority levels 1, 2, and 3; see
Table 13
.
Logic 0 or cleared = default condition.
ISR[0]
INT status.
logic 0 = an interrupt is pending and the ISR contents may be used as
a pointer to the appropriate interrupt service routine
logic 1 = no interrupt pending (normal default condition)
5:4
3:1
0
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