參數(shù)資料
型號: SC16C654BIA68,529
廠商: NXP Semiconductors
文件頁數(shù): 39/58頁
文件大小: 0K
描述: IC QUAD UART 64BYTE 68PLCC
標(biāo)準(zhǔn)包裝: 18
特點(diǎn): 故障啟動(dòng)位檢測
通道數(shù): 4,QUART
FIFO's: 64 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動(dòng)流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 68-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 68-PLCC
包裝: 管件
其它名稱: 935274935529
SC16C654BIA68-S
SC16C654BIA68-S-ND
44
7674F–AVR–09/09
ATmega164P/324P/644P
8.10
Power Reduction Register
The Power Reduction Register(PRR), see “PRR – Power Reduction Register” on page 47, pro-
vides a method to stop the clock to individual peripherals to reduce power consumption. The
current state of the peripheral is frozen and the I/O registers can not be read or written.
Resources used by the peripheral when stopping the clock will remain occupied, hence the
peripheral should in most cases be disabled before stopping the clock. Waking up a module,
which is done by clearing the bit in PRR, puts the module in the same state as before shutdown.
Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall
power consumption. In all other sleep modes, the clock is already stopped.
8.11
Minimizing Power Consumption
There are several issues to consider when trying to minimize the power consumption in an AVR
controlled system. In general, sleep modes should be used as much as possible, and the sleep
mode should be selected so that as few as possible of the device’s functions are operating. All
functions not needed should be disabled. In particular, the following modules may need special
consideration when trying to achieve the lowest possible power consumption.
8.11.1
Analog to Digital Converter
If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be dis-
abled before entering any sleep mode. When the ADC is turned off and on again, the next
conversion will be an extended conversion. Refer to “ADC - Analog-to-digital Converter” on page
243 for details on ADC operation.
8.11.2
Analog Comparator
When entering Idle mode, the Analog Comparator should be disabled if not used. When entering
ADC Noise Reduction mode, the Analog Comparator should be disabled. In other sleep modes,
the Analog Comparator is automatically disabled. However, if the Analog Comparator is set up
to use the Internal Voltage Reference as input, the Analog Comparator should be disabled in all
sleep modes. Otherwise, the Internal Voltage Reference will be enabled, independent of sleep
mode. Refer to “AC - Analog Comparator” on page 240 for details on how to configure the Ana-
log Comparator.
8.11.3
Brown-out Detector
If the Brown-out Detector is not needed by the application, this module should be turned off. If
the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep
modes, and hence, always consume power. In the deeper sleep modes, this will contribute sig-
nificantly to the total current consumption. Refer to “Brown-out Detection” on page 52 for details
on how to configure the Brown-out Detector.
8.11.4
Internal Voltage Reference
The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the
Analog Comparator or the ADC. If these modules are disabled as described in the sections
above, the internal voltage reference will be disabled and it will not be consuming power. When
turned on again, the user must allow the reference to start up before the output is used. If the
reference is kept on in sleep mode, the output can be used immediately. Refer to “Internal Volt-
age Reference” on page 53 for details on the start-up time.
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