參數(shù)資料
型號: SC16C654BIA68,518
廠商: NXP Semiconductors
文件頁數(shù): 48/58頁
文件大小: 0K
描述: IC UART QUAD W/FIFO 68-PLCC
產(chǎn)品培訓模塊: Stand-Alone UARTs
標準包裝: 1
特點: 故障啟動位檢測
通道數(shù): 4,QUART
FIFO's: 64 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 68-LCC(J 形引線)
供應商設備封裝: 68-PLCC
包裝: 剪切帶 (CT)
產(chǎn)品目錄頁面: 828 (CN2011-ZH PDF)
其它名稱: 568-2047
568-2047-ND
52
7674F–AVR–09/09
ATmega164P/324P/644P
Figure 9-2.
External Reset During Operation
9.0.5
Brown-out Detection
ATmega164P/324P/644P has an On-chip Brown-out Detection (BOD) circuit for monitoring the
V
CC level during operation by comparing it to a fixed trigger level. The trigger level for the BOD
can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike
free Brown-out Detection. The hysteresis on the detection level should be interpreted as V
BOT+ =
V
BOT + VHYST/2 and VBOT- = VBOT - VHYST/2.
When the BOD is enabled, and V
CC decreases to a value below the trigger level (VBOT- in Figure
9-3 on page 52), the Brown-out Reset is immediately activated. When V
CC increases above the
trigger level (V
BOT+ in Figure 9-3 on page 52), the delay counter starts the MCU after the
Time-out period t
TOUT has expired.
The BOD circuit will only detect a drop in V
CC if the voltage stays below the trigger level for lon-
ger than t
Figure 9-3.
Brown-out Reset During Operation
9.0.6
Watchdog Reset
When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On
the falling edge of this pulse, the delay timer starts counting the Time-out period t
TOUT. Refer to
page 60 for details on operation of the Watchdog Timer.
CC
VCC
RESET
TIME-OUT
INTERNAL
RESET
VBOT-
VBOT+
tTOUT
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