Philips Semiconductors
SC16C654/654D
Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder
Product data
Rev. 04 — 19 June 2003
9 of 52
9397 750 11617
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
INTA, INTB,
INTC, INTD
15, 21,
49, 55
6, 12,
37, 43
O
Interrupt A, B, C, D (Active-HIGH).
This function is associated with the
16 mode only. These pins provide individual channel interrupts INTA-INTD.
INTA-INTD are enabled when MCR[3] is set to a logic 1, interrupts are enabled
in the interrupt enable register (IER), and when an interrupt condition exists.
Interrupt conditions include: receiver errors, available receiver buffer data,
transmit buffer empty, or when a modem status flag is detected. When the
68 mode is selected, the functions of these pins are re-assigned. 68 mode
functions are described under their respective name/pin headings.
Interrupt Select (Active-HIGH, with internal pull-down).
This function is
associated with the 16 mode only. When the 16 mode is selected, this pin can
be used in conjunction with MCR[3] to enable or disable the 3-State interrupts,
INTA-INTD, or override MCR[3] and force continuous interrupts. Interrupt
outputs are enabled continuously by making this pin a logic 1. Making this pin a
logic 0 allows MCR[3] to control the 3-State interrupt output. In this mode,
MCR[3] is set to a logic 1 to enable the 3-State outputs. This pin is disabled in
the 68 mode. Due to pin limitations on the 64-pin packages, this pin is not
available. To cover this limitation, the SC16C654DIB64 version operates in the
continuous interrupt enable mode by bonding this pin to V
CC
internally. The
SC16C654IB64 operates with MCR[3] control by bonding this pin to GND.
Input/Output Read strobe (Active-LOW).
This function is associated with the
16 mode only. A logic 0 transition on this pin will load the contents of an internal
register defined by address bits A0-A2 onto the SC16C654/654D data bus
(D0-D7) for access by external CPU. This pin is disabled in the 68 mode.
Input/Output Write strobe (Active-LOW).
This function is associated with the
16 mode only. A logic 0 transition on this pin will transfer the contents of the
data bus (D0-D7) from the external CPU to an internal register that is defined
by address bits A0-A2. When the 16 mode is selected (PLCC68), this pin
functions as R/W (see definition under R/W).
Interrupt Request or Interrupt ‘A’.
This function is associated with the
68 mode only. In the 68 mode, interrupts from UART channels A-D are
wire-ORed internally to function as a single IRQ interrupt. This pin transitions to
a logic 0 (if enabled by the interrupt enable register) whenever a UART
channel(s) requires service. Individual channel interrupt status can be
determined by addressing each channel through its associated internal
register, using CS and A3-A4. In the 68 mode, and external pull-up resistor
must be connected between this pin and V
CC
. The function of this pin changes
to INTA when operating in the 16 mode (see definition under INTA).
Not connected.
INTSEL
65
-
I
IOR
52
40
I
IOW
18
9
I
IRQ
15
-
O
NC
21, 49,
52, 54,
55, 65
37
-
-
RESET,
RESET
27
I
Reset.
In the 16 mode, a logic 1 on this pin will reset the internal registers and
all the outputs. The UART transmitter output and the receiver input will be
disabled during reset time. (See
Section 7.11 “SC16C654/654D external reset
conditions”
for initialization details.) When 16/68 is a logic 0 (68 mode), this pin
functions similarly, bus as an inverted reset interface signal, RESET.
Ring Indicator (Active-LOW).
These inputs are associated with individual
UART channels, A through D. A logic 0 on this pin indicates the modem has
received a ringing signal from the telephone line. A logic 1 transition on this
input pin will generate an interrupt.
RIA, RIB,
RIC, RID
8, 28,
42, 62
63, 19,
30, 50
I
Table 2:
Pin description
…continued
Pin
PLCC68 LQFP64
Symbol
Type
Description