參數(shù)資料
型號(hào): SC16C652IB48
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Dual UART with 32 bytes of transmit and receive FIFOs
中文描述: 2 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PQFP48
封裝: 7 X 7 MM, 1.40 MM HEIGHT, MS-026, SOT313-2, LQFP-48
文件頁(yè)數(shù): 22/41頁(yè)
文件大?。?/td> 575K
代理商: SC16C652IB48
Philips Semiconductors
SC16C652
Dual UART with 32 bytes of transmit and receive FIFOs
Product data
Rev. 04 — 20 June 2003
22 of 41
9397 750 11634
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.6 Modem Control Register (MCR)
This register controls the interface with the modem or a peripheral device.
Table 20:
Bit
7
Modem Control Register bits description
Symbol
Description
MCR[7]
Clock select
Logic 0 = Divide by 1 clock input.
Logic 1 = Divide by 4 clock input.
MCR[6]
Reserved; set to ‘0’.
MCR[5]
Reserved; set to ‘0’.
MCR[4]
Loop-back. Enable the local loop-back mode (diagnostics). In this
mode the transmitter output (TX) and the receiver input (RX), CTS,
DSR, CD, and RI are disconnected from the SC16C652 I/O pins.
Internally the modem data and control pins are connected into a
loop-back data configuration (see
Figure 4
). In this mode, the receiver
and transmitter interrupts remain fully operational. The Modem
Control Interrupts are also operational, but the interrupts’ sources are
switched to the lower four bits of the Modem Control. Interrupts
continue to be controlled by the IER register.
Logic 0 = Disable loop-back mode (normal default condition).
Logic 1 = Enable local loop-back mode (diagnostics).
MCR[3]
OP2/INT enable
Logic 0 = Forces INT (A-B) outputs to the 3-State mode and sets
OP2 to a logic 1 (normal default condition).
Logic 1 = Forces the INT (A-B outputs to the active mode and sets
OP2 to a logic 0.
MCR[2]
(OP1). OP1A/OP1B are not available as an external signal in the
SC16C652. This bit is instead used in the Loop-back mode only. In
the loop-back mode, this bit is used to write the state of the modem RI
interface signal.
MCR[1]
RTS
Logic 0 = Force RTS output to a logic 1 (normal default condition).
Logic 1 = Force RTS output to a logic 0.
MCR[0]
DTR
Logic 0 = Force DTR output to a logic 1 (normal default condition).
Logic 1 = Force DTR output to a logic 0.
6
5
4
3
2
1
0
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