Updated and changed “On-chip Debug System” to
參數(shù)資料
型號: SC16C652BIBS,157
廠商: NXP Semiconductors
文件頁數(shù): 11/21頁
文件大?。?/td> 0K
描述: IC UART DUAL W/FIFO 32HVQFN
產(chǎn)品培訓(xùn)模塊: Stand-Alone UARTs
標準包裝: 2,450
特點: 2 通道
通道數(shù): 2,DUART
FIFO's: 32 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-HVQFN(5x5)
包裝: 托盤
其它名稱: 568-2046
935276387157
SC16C652BIBS
19
2503QS–AVR–02/11
ATmega32(L)
Changes from Rev.
2503D-02/03 to
Rev. 2503E-09/03
1.
Updated and changed “On-chip Debug System” to “JTAG Interface and On-chip
Debug System” on page 35.
2.
Updated Table 15 on page 37.
3.
Updated “Test Access Port – TAP” on page 219 regarding the JTAGEN fuse.
4.
Updated description for Bit 7 – JTD: JTAG Interface Disable on page 228.
5.
Added a note regarding JTAGEN fuse to Table 104 on page 257.
6.
Updated Absolute Maximum Ratings* , DC Characteristics and ADC Characteristics in
“Electrical Characteristics” on page 287.
7.
Added a proposal for solving problems regarding the JTAG instruction
IDCODE in
“Errata” on page 336
.
Changes from Rev.
2503C-10/02 to
Rev. 2503D-02/03
1.
Added EEAR9 in EEARH in “Register Summary” on page 327.
2.
Added Chip Erase as a first step in“Programming the Flash” on page 284 and “Pro-
gramming the EEPROM” on page 285.
3.
Removed reference to “Multi-purpose Oscillator” application note and “32 kHz Crys-
tal Oscillator” application note, which do not exist.
4.
Added information about PWM symmetry for Timer0 and Timer2.
5.
Added note in “Filling the Temporary Buffer (Page Loading)” on page 251 about writ-
ing to the EEPROM during an SPM Page Load.
6.
Added “Power Consumption” data in “Features” on page 1.
7.
Added section “EEPROM Write During Power-down Sleep Mode” on page 22.
8.
Added note about Differential Mode with Auto Triggering in “Prescaling and Conver-
sion Timing” on page 204.
9.
Updated Table 89 on page 232.
10.Added updated “Packaging Information” on page 333.
Changes from Rev.
2503B-10/02 to
Rev. 2503C-10/02
1.
Updated the “DC Characteristics” on page 287.
Changes from Rev.
2503A-03/02 to
Rev. 2503B-10/02
1.
Canged the endurance on the Flash to 10,000 Write/Erase Cycles.
2.
Bit nr.4 – ADHSM – in SFIOR Register removed.
3.
Added the section “Default Clock Source” on page 25.
4.
When using External Clock there are some limitations regards to change of fre-
quency. This is described in “External Clock” on page 31 and Table 117 on page 289.
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