參數(shù)資料
型號: SC16C652BIB48,128
廠商: NXP Semiconductors
文件頁數(shù): 7/21頁
文件大?。?/td> 0K
描述: IC ENCODER/DECODER IRDA 48LQFP
標(biāo)準(zhǔn)包裝: 2,000
特點: 2 通道
通道數(shù): 2,DUART
FIFO's: 32 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 帶卷 (TR)
其它名稱: 935274409128
SC16C652BIB48-F
SC16C652BIB48-F-ND
SC16C652B_4
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 04 — 1 September 2005
15 of 43
Philips Semiconductors
SC16C652B
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
7.
Register descriptions
Table 9 details the assigned bit functions for the SC16C652B internal registers. The
assigned bit functions are more fully dened in Section 7.1 through Section 7.11.
[1]
The value shown in represents the register’s initialized HEX value; X = not applicable.
[2]
This bit is only accessible when EFR[4] is set.
[3]
Accessible only when LCR[7] is logic 0.
[4]
Baud rate registers accessible only when LCR[7] is logic 1.
[5]
Enhanced Feature Register, Xon1/Xon2 and Xoff1/Xoff2 are accessible only when LCR is set to ‘BFh’.
Table 9:
SC16C652B internal registers
A2 A1 A0 Register Default [1] Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
General Register Set [3]
0
RHR
XX
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0
THR
XX
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0
1
IER
00
CTS
interrupt
RTS
interrupt
Xoff
interrupt
Sleep
mode [2]
modem
status
interrupt
Rx
receive
line
status
interrupt
transmit
holding
register
interrupt
receive
holding
register
0
1
0
FCR
00
RCVR
trigger
(MSB)
RCVR
trigger
(LSB)
TX
trigger
(MSB) [2]
TX trigger
DMA
mode
select
XMIT
FIFO
reset
RCVR
FIFO
reset
FIFOs
enable
0
1
0
ISR
01
FIFOs
enabled
FIFOs
enabled
INT
priority
bit 4
INT
priority
bit 3
INT
priority
bit 2
INT
priority
bit 1
INT
priority
bit 0
INT
status
0
1
LCR
00
divisor
latch
enable
set break set parity
even
parity
enable
stop bits
word
length
bit 1
word
length
bit 0
1
0
MCR
00
clock
select [2]
IRDA
enable
0
loop back OP2/INT
enable
(OP1)
RTS
DTR
1
0
1
LSR
60
FIFO
data
error
THR and
TSR
empty
THR
empty
break
interrupt
framing
error
parity
error
overrun
error
receive
data
ready
1
0
MSR
X0
CD
RI
DSR
CTS
CD
RI
DSR
CTS
1
SPR
FF
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Special Register Set [4]
0
DLL
XX
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0
1
DLM
XX
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Enhanced Register Set [5]
0
1
0
EFR
00
Auto
CTS
Auto RTS special
character
select
Enable
IER[7:4],
ISR[5:4],
FCR[5:4],
MCR[7:5]
Cont-3
Tx, Rx
Control
Cont-2
Tx, Rx
Control
Cont-1
Tx, Rx
Control
Cont-0
Tx, Rx
Control
1
0
Xon-1
00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
1
0
1
Xon-2
00
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
1
0
Xoff-1
00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
1
Xoff-2
00
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
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