參數(shù)資料
型號(hào): SC16C652
廠商: NXP Semiconductors N.V.
英文描述: Dual UART with 32 bytes of transmit and receive FIFOs
中文描述: 雙UART,有32發(fā)送和接收FIFO字節(jié)
文件頁數(shù): 15/41頁
文件大?。?/td> 575K
代理商: SC16C652
Philips Semiconductors
SC16C652
Dual UART with 32 bytes of transmit and receive FIFOs
Product data
Rev. 04 — 20 June 2003
15 of 41
9397 750 11634
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.1 Transmit (THR) and Receive (RHR) Holding Registers
The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and
Transmit Shift Register (TSR). The status of the THR is provided in the Line Status
Register (LSR). Writing to the THR transfers the contents of the data bus (D7-D0) to
the TSR and UART via the THR, providing that the THR is empty. The THR empty
flag in the LSR register will be set to a logic 1 when the transmitter is empty or when
data is transferred to the TSR. Note that a write operation can be performed when the
THR empty flag is set (logic 0 = at least one byte in FIFO/THR, logic 1 = FIFO/THR
empty).
The serial receive section also contains an 8-bit Receive Holding Register (RHR) and
a Receive Serial Shift Register (RSR). Receive data is removed from the SC16C652
and receive FIFO by reading the RHR register. The receive section provides a
mechanism to prevent false starts. On the falling edge of a start or false start bit, an
internal receiver counter starts counting clocks at the 16
×
clock rate. After 7-
1
2
clocks, the start bit time should be shifted to the center of the start bit. At this time the
start bit is sampled, and if it is still a logic 0 it is validated. Evaluating the start bit in
this manner prevents the receiver from assembling a false character. Receiver status
codes will be posted in the LSR.
7.2 Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) masks the interrupts from receiver ready,
transmitter empty, line status and modem status registers. These interrupts would
normally be seen on the INTA, INTB output pins.
Table 10:
Bit
7
Interrupt Enable Register bits description
Symbol
Description
IER[7]
CTS interrupt.
Logic 0 = Disable the CTS interrupt (normal default condition).
Logic 1 = Enable the CTS interrupt. The SC16C652 issues an
interrupt when the CTS pin transitions from a logic 0 to a logic 1.
IER[6]
RTS interrupt.
Logic 0 = Disable the RTS interrupt (normal default condition).
Logic 1 = Enable the RTS interrupt. The SC16C652 issues an
interrupt when the RTS pin transitions from a logic 0 to a logic 1.
IER[5]
Xoff interrupt.
Logic 0 = Disable the software flow control, receive Xoff interrupt
(normal default condition).
Logic 1 = Enable the software flow control, receive Xoff
interrupt.
IER[4]
Sleep mode.
Logic 0 = Disable sleep mode (normal default condition).
Logic 1 = Enable sleep mode.
IER[3]
Modem Status Interrupt. This interrupt will be issued whenever
there is a modem status change as reflected in MSR[0-3].
Logic 0 = Disable the modem status register interrupt (normal
default condition).
Logic 1 = Enable the modem status register interrupt.
6
5
4
3
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