參數(shù)資料
型號(hào): SC16C650BIB48
廠商: NXP Semiconductors N.V.
元件分類: 收發(fā)器
英文描述: 5 V, 3.3 V and 2.5 V UART with 32-byte FIFOs and infrared (IrDA) encoder-decoder
封裝: SC16C650BIB48<SOT313-2 (LQFP48)|<<http://www.nxp.com/packages/SOT313-2.html<1<Always Pb-free,;SC16C650BIB48<SOT313-2 (LQFP48)|<<http://www.nxp.com/packages/SOT313-2.html&
文件頁(yè)數(shù): 23/48頁(yè)
文件大?。?/td> 241K
代理商: SC16C650BIB48
SC16C650B_4
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 14 September 2009
23 of 48
NXP Semiconductors
SC16C650B
UART with 32-byte FIFOs and IrDA encoder/decoder
7.6 Modem Control Register (MCR)
This register controls the interface with the modem or a peripheral device.
Table 16.
LCR[5]
X
0
0
1
1
LCR[5] parity selection
LCR[4]
X
0
1
0
1
LCR[3]
0
1
1
1
1
Parity selection
no parity
odd parity
even parity
force parity ‘1’
forced parity ‘0’
Table 17.
LCR[2]
0
1
1
LCR[2] stop bit length
Word length
5, 6, 7, 8
5
6, 7, 8
Stop bit length (bit times)
1
1-
1
2
2
Table 18.
LCR[1]
0
0
1
1
LCR[1:0] word length
LCR[0]
0
1
0
1
Word length
5
6
7
8
Table 19.
Bit
7
Modem Control Register bits description
Symbol
Description
MCR[7]
Clock select.
logic 0 = divide-by-1. The input clock (crystal or external) is divided by 16 and
then presented to the programmable Baud Rate Generator (BGR) without
further modification, i.e., divide-by-1 (normal default condition).
logic 1 = divide-by-4. The divide-by-1 clock described in MCR[7] equals a
logic 0, is further divided by four (see also
Section 6.7 “Programmable baud
rate generator”
).
MCR[6]
IR enable.
logic 0 = enable the standard modem receive and transmit input/output
interface (normal default condition)
logic 1 = enable infrared IrDA receive and transmit inputs/outputs. While in this
mode, the TX/RX output/inputs are routed to the infrared encoder/decoder.
The data input and output levels will conform to the IrDA infrared interface
requirement. As such, while in this mode, the infrared TX output will be a
logic 0 during idle data conditions.
6
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