參數(shù)資料
型號(hào): SC16C650BIB48,157
廠商: NXP Semiconductors
文件頁(yè)數(shù): 10/48頁(yè)
文件大?。?/td> 0K
描述: IC UART SOT313-2
標(biāo)準(zhǔn)包裝: 1,250
通道數(shù): 1,UART
FIFO's: 32 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動(dòng)流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類(lèi)型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 托盤(pán)
其它名稱(chēng): 935274391157
SC16C650BIB48
SC16C650BIB48-ND
SC16C650B_4
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 14 September 2009
18 of 48
NXP Semiconductors
SC16C650B
UART with 32-byte FIFOs and IrDA encoder/decoder
7.2.1 IER versus receive FIFO interrupt mode operation
When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1) are
enabled, the receive interrupts and register status will reect the following:
The receive data available interrupts are issued to the external CPU when the FIFO
has reached the programmed trigger level. It will be cleared when the FIFO drops
below the programmed trigger level.
FIFO status will also be reected in the user accessible ISR register when the FIFO
trigger level is reached. Both the ISR register status bit and the interrupt will be
cleared when the FIFO drops below the trigger level.
The data ready bit (LSR[0]) is set as soon as a character is transferred from the shift
register to the receive FIFO. It is reset when the FIFO is empty.
7.2.2 IER versus receive/transmit FIFO polled mode operation
When FCR[0] = logic 1, resetting IER[3:0] enables the SC16C650B in the FIFO polled
mode of operation. Since the receiver and transmitter have separate bits in the LSR,
either or both can be used in the polled mode by selecting respective transmit or receive
control bit(s).
LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.
LSR[4:1] will provide the type of errors encountered, if any.
LSR[5] will indicate when the transmit FIFO is empty.
LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty.
LSR[7] will indicate any FIFO data errors.
2
IER[2]
Receive Line Status interrupt. This interrupt will be issued whenever a fully
assembled receive character is transferred from RSR to the RHR/FIFO, i.e.,
data ready, LSR[0].
logic 0 = disable the receiver line status interrupt (normal default condition)
logic 1 = enable the receiver line status interrupt
1
IER[1]
Transmit Holding Register interrupt. This interrupt will be issued whenever the
THR is empty, and is associated with LSR[1].
logic 0 = disable the transmitter empty interrupt (normal default condition)
logic 1 = enable the transmitter empty interrupt
0
IER[0]
Receive Holding Register interrupt. This interrupt will be issued when the FIFO
has reached the programmed trigger level, or is cleared when the FIFO drops
below the trigger level in the FIFO mode of operation.
logic 0 = disable the receiver ready interrupt (normal default condition)
logic 1 = enable the receiver ready interrupt
Table 9.
Interrupt Enable Register bits description …continued
Bit
Symbol
Description
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