參數(shù)資料
型號： SC16C650A
廠商： NXP Semiconductors N.V.
英文描述： Universal Asynchronous Receiver/Transmitter (UART) with 32-byte FIFO and infrared (IrDA) encoder/decoder
中文描述： 通用異步接收器/發(fā)送器（UART）與32字節(jié)的FIFO和紅外（IrDA）編碼器/解碼器
文件頁數(shù)： 17/50頁
文件大?。?/td> 642K
代理商： SC16C650A
Philips Semiconductors
SC16C650A
UART with 32-byte FIFO and IrDA encoder/decoder
Product data
Rev. 04 — 20 June 2003
17 of 50
9397 750 11622
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.
Register descriptions
Table 8
details the assigned bit functions for the fifteen SC16C650A internal registers.
The assigned bit functions are more fully defined in
Section 7.1
through
Section 7.11
.
[1]
[2]
[3]
[4]
The value shown represents the register’s initialized HEX value; X = n/a.
These registers are accessible only when LCR[7] = 0.
The Special Register set is accessible only when LCR[7] is set to a logic 1.
Enhanced Feature Register, Xon-1,2 and Xoff-1,2 are accessible only when LCR is set to ‘BF
Hex
’.
Table 8:
Shaded bits are only accessible when EFR[4] is set.
A2
A1
A0
Register Default
[1]
Bit 7
General Register Set
[2]
0
0
0
RHR
0
0
0
THR
0
0
1
IER
SC16C650A internal registers
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
XX
XX
00
bit 7
bit 7
CTS
interrupt
bit 6
bit 6
RTS
interrupt
bit 5
bit 5
Xoff
interrupt
bit 4
bit 4
Sleep
mode
bit 3
bit 3
modem
status
interrupt
DMA
mode
select
INT
priority
bit 2
parity
enable
bit 2
bit 2
receive
linestatus
interrupt
XMIT
FIFO
reset
INT
priority
bit 1
stop bits
bit 1
bit 1
transmit
holding
register
RCVR
FIFO
reset
INT
priority
bit 0
word
length
bit 1
RTS
bit 0
bit 0
receive
holding
register
FIFO
enable
0
1
0
FCR
00
RCVR
trigger
(MSB)
FIFOs
enabled
RCVR
trigger
(LSB)
FIFOs
enabled
TX
trigger
(MSB)
INT
priority
bit 4
TXtrigger
(LSB)
0
1
0
ISR
01
INT
priority
bit 3
INT
status
0
1
1
LCR
00
divisor
latch
enable
Clock
select
set break set parity even
parity
word
length
bit 0
DTR
1
0
0
MCR
00
IR enable INT type
select
loop back OUT2,
INT
enable
framing
error
OUT1
1
0
1
LSR
60
FIFO
data
error
DCD
bit 7
trans.
empty
trans.
holding
empty
DSR
bit 5
break
interrupt
parity
error
overrun
error
receive
data
ready
CTS
bit 0
1
1
Special Register Set
[3]
0
0
0
0
0
1
Enhanced Register Set
[4]
0
1
0
1
1
0
1
MSR
SPR
X0
FF
RI
bit 6
CTS
bit 4
DCD
bit 3
RI
bit 2
DSR
bit 1
DLL
DLM
XX
XX
bit 7
bit 15
bit 6
bit 14
bit 5
bit 13
bit 4
bit 12
bit 3
bit 11
bit 2
bit 10
bit 1
bit 9
bit 0
bit 8
EFR
00
Auto
CTS
Auto RTS Special
char.
select
Enable
IER[4-7],
ISR[4,5],
FCR[4,5],
MCR[5-7]
bit 4
bit 12
bit 4
bit 12
Cont-3
Tx, Rx
Control
Cont-2
Tx, Rx
Control
Cont-1
Tx, Rx
Control
Cont-0
Tx, Rx
Control
1
1
1
1
0
0
1
1
0
1
0
1
Xon-1
Xon-2
Xoff-1
Xoff-2
00
00
00
00
bit 7
bit 15
bit 7
bit 15
bit 6
bit 14
bit 6
bit 14
bit 5
bit 13
bit 5
bit 13
bit 3
bit 11
bit 3
bit 11
bit 2
bit 10
bit 2
bit 10
bit 1
bit 9
bit 1
bit 9
bit 0
bit 8
bit 0
bit 8
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