參數(shù)資料
型號： SC16C554IB80,557
廠商： NXP Semiconductors
文件頁數(shù)： 27/55頁
文件大?。?/td> 0K
描述： IC UART QUAD SOT315-1
標準包裝： 595
通道數(shù)： 4，QUART
FIFO's： 16 字節(jié)
電源電壓： 2.5V，3.3V，5V
帶自動流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
帶調制解調器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 80-LQFP
供應商設備封裝： 80-LQFP（12x12）
包裝： 托盤
其它名稱： 935270075557
SC16C554IB80
SC16C554IB80-ND
Philips Semiconductors
SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Product data
Rev. 05 — 10 May 2004
33 of 55
9397 750 13132
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
[1]
Whenever any MSR bit 0-3 is set to logic 1, a Modem Status Interrupt will be generated.
7.9 Scratchpad Register (SPR)
The SC16C554/554D provides a temporary data register to store 8 bits of user
information.
7.10 Enhanced Feature Register (EFR)
Enhanced features are enabled or disabled using this register.
Bits 0 through 4 provide single or dual character software ow control selection.
When the Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double
8-bit words are concatenated into two sequential numbers.
1
MSR[1]
DSR [1]
Logic 0 = No DSR change (normal default condition).
Logic1=The DSR input to the SC16C554/554D has changed state
since the last time it was read. A modem Status Interrupt will be
generated.
0
MSR[0]
CTS [1]
Logic 0 = No CTS change (normal default condition).
Logic 1 = The CTS input to the SC16C554/554D has changed state
since the last time it was read. A modem Status Interrupt will be
generated.
Table 20:
Modem Status Register bits description…continued
Bit
Symbol
Description
Table 21:
Enhanced Feature Register bits description
Bit
Symbol
Description
7
EFR[7]
Auto CTS. Automatic CTS Flow Control.
Logic 0 = Automatic CTS ow control is disabled (normal default
condition).
Logic 1 = Enable Automatic CTS ow control. Transmission will stop
when CTS goes to a logical 1. Transmission will resume when the CTS
pin returns to a logical 0.
6
EFR[6]
Auto RTS. Automatic RTS may be used for hardware ow control by
enabling EFR[6]. When Auto RTS is selected, an interrupt will be
generated when the receive FIFO is lled to the programmed trigger
level and RTS will go to a logic 1 at the next trigger level. RTS will return
to a logic 0 when data is unloaded below the next lower trigger level.
The state of this register bit changes with the status of the hardware ow
control. RTS functions normally when hardware ow control is disabled.
Logic 0 = Automatic RTS ow control is disabled (normal default
condition).
Logic 1 = Enable Automatic RTS ow control.
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