參數(shù)資料
型號: SC16C554DBIB64,151
廠商: NXP Semiconductors
文件頁數(shù): 45/57頁
文件大?。?/td> 0K
描述: IC UART QUAD W/FIFO 64-LQFP
產(chǎn)品培訓(xùn)模塊: Stand-Alone UARTs
標(biāo)準(zhǔn)包裝: 160
通道數(shù): 4,QUART
FIFO's: 16 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動流量控制功能:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤
產(chǎn)品目錄頁面: 827 (CN2011-ZH PDF)
其它名稱: 568-3270
935276669151
SC16C554DBIB64-S
PIC12(L)F1822/PIC16(L)F1823
DS41413C-page 50
2010-2012 Microchip Technology Inc.
REGISTER 4-1:
CONFIGURATION WORD 1
R/P-1/1
FCMEN
IESO
CLKOUTEN
BOREN<1:0>
CPD
bit 13
bit 8
R/P-1/1
CP
MCLRE
PWRTE
WDTE<1:0>
FOSC<2:0>
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared
‘1’ = Bit is set
-n = Value when blank or after Bulk Erase
bit 13
FCMEN:
Fail-Safe Clock Monitor Enable bit
1
= Fail-Safe Clock Monitor is enabled
0
= Fail-Safe Clock Monitor is disabled
bit 12
IESO:
Internal External Switchover bit
1
= Internal/External Switchover mode is enabled
0
= Internal/External Switchover mode is disabled
bit 11
CLKOUTEN:
Clock Out Enable bit
If FOSC configuration bits are set to LP, XT, HS modes:
This bit is ignored, CLKOUT function is disabled. Oscillator function on the CLKOUT pin
All other FOSC modes:
1
= CLKOUT function is disabled. I/O function on the CLKOUT pin
0
= CLKOUT function is enabled on the CLKOUT pin
bit 10-9
BOREN<1:0>:
Brown-out Reset Enable bits(1)
11
= BOR enabled
10
= BOR enabled during operation and disabled in Sleep
01
= BOR controlled by SBOREN bit of the BORCON register
00
= BOR disabled
bit 8
CPD:
Data Code Protection bit(2)
1
= Data memory code protection is disabled
0
= Data memory code protection is enabled
bit 7
CP:
Code Protection bit(3)
1
= Program memory code protection is disabled
0
= Program memory code protection is enabled
bit 6
MCLRE:
MCLR/VPP Pin Function Select bit
If LVP bit = 1:
This bit is ignored.
If LVP bit = 0:
1
=MCLR/VPP pin function is MCLR; Weak pull-up enabled.
0
=MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of the WPUA
register.
bit 5
PWRTE:
Power-up Timer Enable bit(1)
1
= PWRT disabled
0
= PWRT enabled
bit 4-3
WDTE<1:0>:
Watchdog Timer Enable bit
11
= WDT enabled
10
= WDT enabled while running and disabled in Sleep
01
= WDT controlled by the SWDTEN bit in the WDTCON register
00
= WDT disabled
Note
1:
Enabling Brown-out Reset does not automatically enable Power-up Timer.
2:
The entire data EEPROM will be erased when the code protection is turned off during an erase.
3:
The entire program memory will be erased when the code protection is turned off.
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