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參數(shù)資料
型號: SC16C554BIBM,151
廠商: NXP Semiconductors
文件頁數(shù): 29/57頁
文件大?。?/td> 0K
描述: IC UART QUAD W/FIFO 64-LQFP
產(chǎn)品培訓模塊: Stand-Alone UARTs
標準包裝: 250
通道數(shù): 4,QUART
FIFO's: 16 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動流量控制功能:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應商設備封裝: 64-LQFP(7x7)
包裝: 托盤
產(chǎn)品目錄頁面: 827 (CN2011-ZH PDF)
其它名稱: 568-3267
935279067151
SC16C554BIBM-S
PIC12(L)F1822/PIC16(L)F1823
DS41413C-page 36
2010-2012 Microchip Technology Inc.
Bank 5
280h(1)
INDF0
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
281h(1)
INDF1
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
282h(1)
PCL
Program Counter (PC) Least Significant Byte
0000 0000 0000 0000
283h(1)
STATUS
—TO
PD
ZDC
C
---1 1000 ---q quuu
284h(1)
FSR0L
Indirect Data Memory Address 0 Low Pointer
0000 0000 uuuu uuuu
285h(1)
FSR0H
Indirect Data Memory Address 0 High Pointer
0000 0000 0000 0000
286h(1)
FSR1L
Indirect Data Memory Address 1 Low Pointer
0000 0000 uuuu uuuu
287h(1)
FSR1H
Indirect Data Memory Address 1 High Pointer
0000 0000 0000 0000
288h(1)
BSR
BSR<4:0>
---0 0000 ---0 0000
289h(1)
WREG
Working Register
0000 0000 uuuu uuuu
28Ah(1)
PCLATH
Write Buffer for the upper 7 bits of the Program Counter
-000 0000 -000 0000
28Bh(1)
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
0000 000x 0000 000u
28Ch
Unimplemented
28Dh
Unimplemented
28Eh
Unimplemented
28Fh
Unimplemented
290h
Unimplemented
291h
CCPR1L
Capture/Compare/PWM Register 1 (LSB)
xxxx xxxx uuuu uuuu
292h
CCPR1H
Capture/Compare/PWM Register 1 (MSB)
xxxx xxxx uuuu uuuu
293h
CCP1CON
P1M<1:0>
DC1B<1:0>
CCP1M<3:0>
0000 0000 0000 0000
294h
PWM1CON
P1RSEN
P1DC<6:0>
0000 0000 0000 0000
295h
CCP1AS
CCP1ASE
CCP1AS<2:0>
PSS1AC<1:0>
PSS1BD<1:0>
0000 0000 0000 0000
296h
PSTR1CON
STR1SYNC
STR1D
STR1C
STR1B
STR1A
---0 0001 ---0 0001
297h
Unimplemented
298h
Unimplemented
299h
Unimplemented
29Ah
Unimplemented
29Bh
Unimplemented
29Ch
Unimplemented
29Dh
Unimplemented
29Eh
Unimplemented
29Fh
Unimplemented
TABLE 3-8:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Legend:
x
= unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note
1:
These registers can be addressed from any bank.
2:
PIC16(L)F1823 only.
3:
Unimplemented. Read as ‘1’.
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