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| 型號： | SC16C550IB48 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Universal Asynchronous Receiver/Transmitter (UART) with 16-byte FIFO and infrared (IrDA) encoder/decoder |
| 中文描述： | 1 CHANNEL(S), 3M bps, SERIAL COMM CONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-313-2, LQFP-48 |
| 文件頁數(shù)： | 7/52頁 |
| 文件大?。?/td> | 639K |
| 代理商： | SC16C550IB48 |
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Philips Semiconductors
SC16C550
UART with 16-byte FIFO and IrDA encoder/decoder
Product data
Rev. 05 — 19 June 2003
7 of 52
9397 750 11619
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
CS0, CS1,
CS2
14, 15,
16
9, 10,
11
12,13,
14
I
Chip select.
When CS0 and CS1 are HIGH and CS2 is LOW, these
three inputs select the UART. When any of these inputs are inactive,
the UART remains inactive (refer to AS description).
Clear to send.
CTS is a modem status signal. Its condition can be
checked by reading bit 4 (CTS) of the modem status register. Bit 0
(CTS) of the modem status register indicates that CTS has changed
states since the last read from the modem status register. If the
modem status interrupt is enabled when CTS changes levels and the
auto-CTS mode is not enabled, an interrupt is generated. CTS is also
used in the auto-CTS mode to control the transmitter.
Data bus.
Eight data lines with 3-State outputs provide a bi-directional
path for data, control and status information between the UART and
the CPU.
Data carrier detect.
DCD is a modem status signal. Its condition can
be checked by reading bit 7 (DCD) of the modem status register. Bit 3
(DCD) of the modem status register indicates that DCD has changed
states since the last read from the modem status register. If the
modem status interrupt is enabled when DCD changes levels, an
interrupt is generated.
Driver disable.
DDIS is active (LOW) when the CPU is not reading
data. When active, DDIS can disable an external transceiver.
Data set ready.
DSR is a modem status signal. Its condition can be
checked by reading bit 5 (DSR) of the modem status register. Bit 1
(DSR) of the modem status register indicates DSR has changed levels
since the last read from the modem status register. If the modem
status interrupt is enabled when DSR changes levels, an interrupt is
generated.
Data terminal ready.
When active (LOW), DTR informs a modem or
data set that the UART is ready to establish communication. DTR is
placed in the active level by setting the DTR bit of the modem control
register. DTR is placed in the inactive level either as a result of a
Master Reset, during loop mode operation, or clearing the DTR bit.
Interrupt.
When active (HIGH), INT informs the CPU that the UART
has an interrupt to be serviced. Four conditions that cause an interrupt
to be issued are: a receiver error, received data that is available or
timed out (FIFO mode only), an empty transmitter holding register or
an enabled modem status interrupt. INT is reset (deactivated) either
when the interrupt is serviced or as a result of a Master Reset.
Master Reset.
When active (HIGH), MR clears most UART registers
and sets the levels of various output signals.
Not connected.
CTS
40
38
36
I
D7-D0
2-9
43-47,
2-4
8-1
I/O
DCD
42
40
38
I
DDIS
26
22
23
O
DSR
41
39
37
I
DTR
37
33
33
O
INT
33
30
30
O
MR
39
35
35
I
NC
1, 12,
23, 34
1, 5, 13,
21, 25,
36, 37,
48
34, 31
-
-
OUT1, OUT2 38, 35
34, 31
O
Outputs 1 and 2.
These are user-designated output terminals that are
set to the active (low) level by setting respective modem control
register (MCR) bits (OUT1 and OUT2). OUT1 and OUT2 are set to
inactive the (HIGH) level as a result of Master Reset, during loop mode
operations, or by clearing bit 2 (OUT1) or bit 3 (OUT2) of the MCR.
Table 2:
Symbol
Pin description
…continued
Pin
PLCC44 LQFP48 DIP40
Type
Description
相關(guān)PDF資料 |
PDF描述 |
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| SC16C554IB64 | Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder |
| SC16C554 | Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder |
| SC16C554DB | 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs |
| SC16C554DIA68 | Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder |
| SC16C554DIB64 | Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SC16C550IB48,128 | 功能描述:UART 接口集成電路 16C 2.5V-5V 1CH UART 16B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C550IB48,151 | 功能描述:UART 接口集成電路 16C 2.5V-5V 1CH UART 16B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C550IB48,157 | 功能描述:UART 接口集成電路 16C 2.5V-5V 1CH UART 16B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C550IN40 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Universal Asynchronous Receiver/Transmitter (UART) with 16-byte FIFO and infrared (IrDA) encoder/decoder |
| SC16C550IN40,112 | 功能描述:IC UART SINGLE W/FIFO 40-DIP RoHS:是 類別:集成電路 (IC) >> 接口 - UART（通用異步接收器/發(fā)送器） 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 特點(diǎn):* 通道數(shù):2，DUART FIFO's:16 字節(jié) 規(guī)程:RS232，RS485 電源電壓:2.25 V ~ 5.5 V 帶并行端口:- 帶自動流量控制功能:是 帶IrDA 編碼器/解碼器:是 帶故障啟動位檢測功能:是 帶調(diào)制解調(diào)器控制功能:是 帶CMOS:是 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:托盤 其它名稱:XR16L2551IM-F-ND |
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