參數(shù)資料
型號: SC16C2552BIA44,512
廠商: NXP Semiconductors
文件頁數(shù): 9/37頁
文件大?。?/td> 0K
描述: IC UART DUAL SOT187-2
標(biāo)準(zhǔn)包裝: 26
特點: 2 通道
通道數(shù): 2,DUART
FIFO's: 16 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 44-PLCC
包裝: 管件
其它名稱: 935274408512
SC16C2552BIA44
SC16C2552BIA44-ND
SC16C2552B_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 12 February 2009
17 of 38
NXP Semiconductors
SC16C2552B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
7.5 Line Control Register (LCR)
The Line Control Register is used to specify the asynchronous data communication
format. The word length, the number of stop bits and the parity are selected by writing the
appropriate bits in this register.
Table 12.
Line Control Register bits description
Bit
Symbol
Description
7
LCR[7]
Divisor latch enable. The internal baud rate counter latch and Enhanced
Feature mode enable.
logic 0 = divisor latch disabled (normal default condition)
logic 1 = divisor latch enabled
6
LCR[6]
Set break. When enabled, the Break control bit causes a break condition
to be transmitted (the TX output is forced to a logic 0 state). This
condition exists until disabled by setting LCR[6] to a logic 0.
logic 0 = no TX break condition (normal default condition)
logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the
remote receiver to a line break condition
5:3
LCR[5:3]
Programs the parity conditions (see Table 13)
2
LCR[2]
Stop bits. The length of stop bit is specied by this bit in conjunction with
the programmed word length (see Table 14).
logic 0 or cleared = default condition
1:0
LCR[1:0]
Word length bits 1, 0. These two bits specify the word length to be
transmitted or received (see Table 15).
logic 0 or cleared = default condition
Table 13.
LCR[5:3] parity selection
LCR[5]
LCR[4]
LCR[3]
Parity selection
X
0
no parity
X
0
1
odd parity
0
1
even parity
0
1
forced parity ‘1’
1
forced parity ‘0’
Table 14.
LCR[2] stop bit length
LCR[2]
Word length (bits)
Stop bit length (bit times)
0
5, 6, 7, 8
1
15
11
2
1
6, 7, 8
2
Table 15.
LCR[1:0] word length
LCR[1]
LCR[0]
Word length (bits)
005
016
107
118
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