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參數(shù)資料
| 型號： | SC16C2550IN40 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Dual UART with 16 bytes of transmit and receive FIFOs and infrared (IrDA) encoder/decoder |
| 中文描述： | 2 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PDIP40 |
| 封裝： | 0.600 INCH, PLASTIC, MO-015, SOT-129-1, DIP-40 |
| 文件頁數(shù)： | 20/46頁 |
| 文件大小： | 603K |
| 代理商： | SC16C2550IN40 |
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Philips Semiconductors
SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
Product data
Rev. 03 — 19 June 2003
20 of 46
9397 750 11621
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.3.2
FIFO mode
Table 9:
Bit
7-6
FIFO Control Register bits description
Symbol
Description
FCR[7]
(MSB),
FCR[6]
(LSB)
Logic 1 = RX trigger level.
An interrupt is generated when the number of characters in the
FIFO equals the programmed trigger level. However, the FIFO will
continue to be loaded until it is full. Refer to
Table 10
.
FCR[5-4]
Not used; initialized to logic 0.
FCR[3]
DMA mode select.
Logic 0 = Set DMA mode ‘0’
Logic 1 = Set DMA mode ‘1’
Transmit operation in mode ‘0’:
When the SC16C2550 is in the
16C450 mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO
mode (FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0), and
when there are no characters in the transmit FIFO or transmit
holding register, the TXRDY pin in PLCC44 or LQFP48 packages
will be a logic 0. Once active, the TXRDY pin will go to a logic 1
after the first character is loaded into the transmit holding register.
Receive operation in mode ‘0’:
When the SC16C2550 is in
mode ‘0’ (FCR[0] = logic 0), or in the FIFO mode (FCR[3] = logic 0)
and there is at lease one character in the receive FIFO, the
RXRDY pin will be a logic 0. Once active, the RXRDY pin on
PLCC44 and LQFP48 packages will go to a logic 1 when there are
no more characters in the receiver.
Transmit operation in mode ‘1’:
When the SC16C2550 is in
FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY pin on
PLCC44 and LQFP48 packages will be a logic 1 when the transmit
FIFO is completely full. It will be a logic 0 if one or more FIFO
locations are empty.
Receive operation in mode ‘1’:
When the SC16C2550 is in FIFO
mode (FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has
been reached, or a Receive Time-Out has occurred, the RXRDY
pin on PLCC44 and LQFP48 packages will go to a logic 0. Once
activated, it will go to a logic 1 after there are no more characters in
the FIFO.
FCR[2]
XMIT FIFO reset.
Logic 0 = Transmit FIFO not reset (normal default condition).
Logic 1 = Clears the contents of the transmit FIFO and resets
the FIFO counter logic (the transmit shift register is not cleared
or altered). This bit will return to a logic 0 after clearing the FIFO.
RCVR trigger. These bits are used to set the trigger level for the
receive FIFO interrupt.
Logic 0 (or cleared) = normal default condition.
5-4
3
2
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| SC16C2550IN40,112 | 功能描述:IC UART DUAL W/FIFO 40-DIP RoHS:是 類別:集成電路 (IC) >> 接口 - UART（通用異步接收器/發(fā)送器） 系列:- 標準包裝:250 系列:- 特點:* 通道數(shù):2，DUART FIFO's:16 字節(jié) 規(guī)程:RS232，RS485 電源電壓:2.25 V ~ 5.5 V 帶并行端口:- 帶自動流量控制功能:是 帶IrDA 編碼器/解碼器:是 帶故障啟動位檢測功能:是 帶調(diào)制解調(diào)器控制功能:是 帶CMOS:是 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:托盤 其它名稱:XR16L2551IM-F-ND |
| SC16C2552 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual UART with 16-byte transmit and receive FIFOs |
| SC16C2552B | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs |
| SC16C2552BIA44 | 功能描述:UART 接口集成電路 16CB 2.5V-5V 2CH UART 16B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C2552BIA44,512 | 功能描述:UART 接口集成電路 16CB 2.5V-5V 2CH RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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