參數(shù)資料
型號: SC16C2550IB48
廠商: NXP Semiconductors N.V.
元件分類: 收發(fā)器
英文描述: Dual UART with 16 bytes of transmit and receive FIFOs and infrared (IrDA) encoder-decoder
封裝: SC16C2550IB48<SOT313-2 (LQFP48)|<<http://www.nxp.com/packages/SOT313-2.html<1<week 17, 2005,;
文件頁數(shù): 16/46頁
文件大?。?/td> 603K
代理商: SC16C2550IB48
Philips Semiconductors
SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
Product data
Rev. 03 — 19 June 2003
16 of 46
9397 750 11621
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.
Register descriptions
Table 7
details the assigned bit functions for the SC16C2550 internal registers. The
assigned bit functions are more fully defined in
Section 7.1
through
Section 7.11
.
[1]
[2]
[3]
[4]
The value shown in represents the register’s initialized HEX value; X = n/a.
Accessible only when LCR[7] is logic 0.
Baud rate registers accessible only when LCR[7] is logic 1.
Enhanced Feature Register, Xon-1,2 and Xoff-1,2 are accessible only when LCR is set to ‘BF
Hex
’.
Table 7:
Shaded bits are only accessible when EFR[4] is set.
A2
A1
A0
Register Default
[1]
General Register Set
[2]
0
0
0
RHR
0
0
0
THR
0
0
1
IER
SC16C2550 internal registers
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
XX
XX
00
bit 7
bit 7
CTS
interrupt
bit 6
bit 6
RTS
interrupt
bit 5
bit 5
Xoff
interrupt
bit 4
bit 4
Sleep
mode
bit 3
bit 3
modem
status
interrupt
bit 2
bit 2
receive
line
status
interrupt
XMIT
FIFO
reset
INT
priority
bit 1
stop bits
bit 1
bit 1
transmit
holding
register
interrupt
RCVR
FIFO
reset
INT
priority
bit 0
word
length
bit 1
RTS
bit 0
bit 0
receive
holding
register
0
1
0
FCR
00
RCVR
trigger
(MSB)
FIFOs
enabled
RCVR
trigger
(LSB)
FIFOs
enabled
reserved
0
reserved
0
DMA
mode
select
INT
priority
bit 2
parity
enable
FIFOs
enable
0
1
0
ISR
01
INT
priority
bit 4
INT
priority
bit 3
INT
status
0
1
1
LCR
00
divisor
latch
enable
0
set break set parity even
parity
word
length
bit 0
DTR
1
0
0
MCR
00
IR
enable
THR and
TSR
empty
RI
bit 6
0
loop back OP2/INT
enable
framing
error
(OP1)
1
0
1
LSR
60
FIFO
data
error
CD
bit 7
THR
empty
break
interrupt
parity
error
overrun
error
receive
data
ready
CTS
bit 0
1
1
Special Register Set
[3]
0
0
0
0
0
1
Enhanced Register Set
[4]
0
1
0
1
1
0
1
MSR
SPR
X0
FF
DSR
bit 5
CTS
bit 4
CD
bit 3
RI
bit 2
DSR
bit 1
DLL
DLM
XX
XX
bit 7
bit 15
bit 6
bit 14
bit 5
bit 13
bit 4
bit 12
bit 3
bit 11
bit 2
bit 10
bit 1
bit 9
bit 0
bit 8
EFR
00
Auto
CTS
Auto
RTS
Special
char.
select
Enable
IER[4-7],
ISR[4,5],
FCR[4,5],
MCR[5-7]
bit 4
bit 12
bit 4
bit 12
Cont-3
Tx, Rx
Control
Cont-2
Tx, Rx
Control
Cont-1
Tx, Rx
Control
Cont-0
Tx, Rx
Control
1
1
1
1
0
0
1
1
0
1
0
1
Xon-1
Xon-2
Xoff-1
Xoff-2
00
00
00
00
bit 7
bit 15
bit 7
bit 15
bit 6
bit 14
bit 6
bit 14
bit 5
bit 13
bit 5
bit 13
bit 3
bit 11
bit 3
bit 11
bit 2
bit 10
bit 2
bit 10
bit 1
bit 9
bit 1
bit 9
bit 0
bit 8
bit 0
bit 8
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