參數(shù)資料
型號: SC16C2550BIB48,128
廠商: NXP Semiconductors
文件頁數(shù): 2/31頁
文件大?。?/td> 0K
描述: IC UART DUAL W/FIFO 48-LQFP
標準包裝: 2,000
特點: 故障啟動位檢測
通道數(shù): 2,DUART
FIFO's: 16 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動流量控制功能:
帶故障啟動位檢測功能:
帶調制解調器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應商設備封裝: 48-LQFP(7x7)
包裝: 帶卷 (TR)
其它名稱: 935274406128
SC16C2550BIB48-F
SC16C2550BIB48-F-ND
SC16C2550B_5
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 12 January 2009
10 of 43
NXP Semiconductors
SC16C2550B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
6.2 Internal registers
The SC16C2550B provides two sets of internal registers (A and B) consisting of
12 registers each for monitoring and controlling the functions of each channel of the
UART. These registers are shown in Table 5. The UART registers function as data holding
registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO Control
Register (FCR), line status and control registers (LCR/LSR), modem status and control
registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM) and a
user-accessible Scratchpad Register (SPR).
[1]
These registers are accessible only when LCR[7] is a logic 0.
[2]
These registers are accessible only when LCR[7] is a logic 1.
Table 4.
Serial port selection
Chip Select
Function
CSA, CSB = 1
none
CSA = 0
UART channel A
CSB = 0
UART channel B
Table 5.
Internal registers decoding
A2
A1
A0
READ mode
WRITE mode
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LCR/LSR, SPR)[1]
0
Receive Holding Register
Transmit Holding Register
0
1
Interrupt Enable Register
0
1
0
Interrupt Status Register
FIFO Control Register
0
1
Line Control Register
1
0
Modem Control Register
1
0
1
Line Status Register
n/a
1
0
Modem Status Register
n/a
1
Scratchpad Register
Baud rate register set (DLL/DLM)[2]
0
LSB of Divisor Latch
0
1
MSB of Divisor Latch
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