參數(shù)資料
型號: SC16C2550
廠商: NXP Semiconductors N.V.
英文描述: Dual UART with 16 bytes of transmit and receive FIFOs and infrared (IrDA) encoder/decoder
中文描述: 雙UART具有16字節(jié)的發(fā)送和接收FIFO和紅外線(IrDA)編碼器/解碼器
文件頁數(shù): 21/46頁
文件大小: 603K
代理商: SC16C2550
Philips Semiconductors
SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
Product data
Rev. 03 — 19 June 2003
21 of 46
9397 750 11621
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.4 Interrupt Status Register (ISR)
The SC16C2550 provides four levels of prioritized interrupts to minimize external
software interaction. The Interrupt Status Register (ISR) provides the user with four
interrupt status bits. Performing a read cycle on the ISR will provide the user with the
highest pending interrupt level to be serviced. No other interrupts are acknowledged
until the pending interrupt is serviced. A lower level interrupt may be seen after
servicing the higher level interrupt and re-reading the interrupt status bits.
Table 11
“Interrupt source”
shows the data values (bits 0-3) for the four prioritized interrupt
levels and the interrupt sources associated with each of these interrupt levels.
1
FCR[1]
RCVR FIFO reset.
Logic 0 = Receive FIFO not reset (normal default condition).
Logic 1 = Clears the contents of the receive FIFO and resets the
FIFO counter logic (the receive shift register is not cleared or
altered). This bit will return to a logic 0 after clearing the FIFO.
FIFOs enabled.
Logic 0 = Disable the transmit and receive FIFO (normal default
condition).
Logic 1 = Enable the transmit and receive FIFO.
This bit must
be a ‘1’ when other FCR bits are written to, or they will not
be programmed.
0
FCR[0]
Table 10:
FCR[7]
0
0
1
1
RCVR trigger levels
FCR[6]
0
1
0
1
RX FIFO trigger level
01
04
08
14
Table 9:
Bit
FIFO Control Register bits description
…continued
Symbol
Description
Table 11:
Priority
level
1
Interrupt source
ISR[5]
ISR[4]
ISR[3]
ISR[2]
ISR[1]
ISR[0]
Source of the interrupt
0
0
0
1
1
0
LSR (Receiver Line Status
Register)
RXRDY (Received Data
Ready)
RXRDY (Receive Data
time-out)
TXRDY (Transmitter
Holding Register Empty)
MSR (Modem Status
Register)
RXRDY (Received Xoff
signal) / Special character
CTS, RTS change of state
2
0
0
0
1
0
0
2
0
0
1
1
0
0
3
0
0
0
0
1
0
4
0
0
0
0
0
0
5
0
1
0
0
0
0
6
1
0
0
0
0
0
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