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參數(shù)資料
| 型號： | SC1205CS |
| 廠商： | Semtech Corporation |
| 英文描述： | HIGH SPEED SYNCHRONOUS POWER MOSFET DRIVER |
| 中文描述： | 高速同步功率MOSFET驅(qū)動器 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大小： | 128K |
| 代理商： | SC1205CS |
SC1205
HIGH SPEED SYNCHRONOUS POWER
MOSFET DRIVER
1999 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
PRELIMINARY - December 7, 1999
9
APPLICATION INFORMATION:
SC1205
is a high speed, smart dual MOSFET driver.
It is designed to drive Low Rds_On power MOSFET’s
with ultra-low rise/fall times and propagation delays.
As the switching frequencies of PWM controllers is
increased to reduce power supply and Class-D ampli-
fier volume and cost, fast rise and fall times are nec-
essary to minimize switching losses (TOP MOSFET)
and reduce Dead-time (BOTTOM MOSFET). While
Low Rds_On MOSFET’s present a power saving in I
2
R
losses, the MOSFET’s die area is larger and thus the
effective input capacitance of the MOSFET is in-
creased. Often a 50% decrease in Rds_On more than
doubles the effective input gate charge, which must be
supplied by the driver. The Rds_On power savings
can be offset by the switching and dead-time losses
with a sub-optimum driver. While discrete solution
can achieve reasonable drive capability, implementing
shoot-through, programmable delay and other house-
keeping functions necessary for safe operation can
become cumbersome and costly. The SC120X family
of parts presents a total solution for the high-speed,
high power density applications. Wide input supply
range of 4.5V-25V allows use in battery powered ap-
plications, new high voltage, distributed power servers
as well as Class-D amplifiers.
THEORY OF OPERATION
The control input (CO) to the SC1205 is typically sup-
plied by a PWM controller that regulates the power
supply output. (See Application Evaluation
Schematic, Figure 3). The timing diagram demon-
strates the sequence of events by which the top and
bottom drive signals are applied. The shoot-through
protection is implemented by holding the bottom FET
off until the voltage at the phase node (intersection of
top FET source, the output inductor and the bottom
FET drain) has dropped below 1V. This assures that
the top FET has turned off and that a direct current
path does not exist between the input supply and
ground, a condition which both the top and bottom
FET’s are on momentarily. The top FET is also pre-
vented from turning on until the bottom FET is off.
This time is internally set to 20ns.
LAYOUT GUIDELINES
As with any high speed , high current circuit, proper
layout is critical in achieving optimum performance of
the SC1205. The Evaluation board schematic (Refer
to figure 3) shows a two-phase synchronous design
with all surface mountable components.
While components connecting to EN are relatively
non-critical, tight placement and short,wide traces
must be used in layout of The Drives, DRN, and espe-
cially PGND pin. The top gate driver supply voltage is
provided by bootstrapping the +5V supply and adding
it the phase node voltage (DRN). Since the bootstrap
capacitor supplies the charge to the top gate, it must
be less than .5” away from the SC1205. Ceramic X7R
capacitors are a good choice for supply bypassing
near the chip. The Vcc pin capacitor must also be less
than .5” away from the SC1205. The ground node of
this capacitor, the SC1205 PGND pin and the Source
of the bottom FET must be very close to each other,
preferably with common PCB copper land with multi-
ple vias to the ground plane (if used). The parallel
Shottkey must be physically next to the Bottom FETS
Drain and source. Any trace or lead inductance in
these connections will drive current way from the
Shottkey and allow it to flow through the FET’s Body
diode, thus reducing efficiency.
PREVENTING INADVERTENT BOTTOM FET
TURN-ON
At high input voltages, (12V and greater) a fast turn-on
of the top FET creates a positive going spike on the
Bottom FET’s gate through the Miller capacitance,
crss of the bottom FET. The voltage appearing on the
gate due to this spike is:
Vspike=Vin*crss/(Crass+ciss)
Where Ciss is the input gate capacitance of the bot-
tom FET. This is assuming that the impedance of the
drive path is too high compared to the instantaneous
impedance of the capacitors. (since dV/dT and thus
the effective frequency is very high). If the BG pin of
the SC1205 is very close to the bottom FET, Vspike
will be reduced depending on trace inductance, rate of
rise of current,etc.
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