
394
AMD Geode SC1200/SC1201 Processor Data Book
Electrical Specifications
32579B
9.3.7
Sub-ISA Interface
All output timing is guaranteed for 50 pF load, unless otherwise specified. The ISA Clock divisor (defined in F0 Index
50h[2:0] of the Core Logic module) is 011.
Table 9-24. Sub-ISA Timing Parameters
Symbol
Parameter
Bus
Width
(Bits)
Type
Min
(ns)
Max
(ns)
Figure
Comments
tRD1
MEMR#/DOCR#/RD#/TRDE# read
active pulse width FE to RE
16
M
225
Standard
tRD2
MEMR#/DOCR#/RD#/TRDE# read
active pulse width FE to RE
16
M
105
Zero wait state
tRD3
IOR#/RD#/TRDE# read active pulse
width FE to RE
16
I/O
160
Standard
tRD4
IOR#/MEMR#/DOCR#/RD#/TRDE#
read active pulse width FE to RE
8
M, I/O
520
Standard
tRD5
IOR#/MEMR#/DOCR#/RD#/TRDE#
read active pulse width FE to RE
8
M, I/O
160
Zero wait state
tRCU1
MEMR#/DOCR#/RD#/TRDE#
inactive pulse width
16
M
103
tRCU2
MEMR#/DOCR#/RD#/TRDE#
inactive pulse width
8M
163
tRCU3
IOR#/RD#/TRDE# inactive pulse
width
8, 16
I/O
163
tWR1
MEMW#/WR# write active pulse
width FE to RE
16
M
225
Standard
tWR2
MEMW#/DOCW#/WR# write active
pulse width FE to RE
16
M
105
Zero wait state
tWR3
IOW#/WR# write active pulse width
FE to RE
16
I/O
160
Standard
tWR4
IOW#/MEMW#/DOCW#/WR# write
active pulse width FE to RE
8
M, I/O
520
Standard
tWR5
IOW#/MEMW#/DOCW#/WR# write
active pulse width FE to RE
8
M, I/O
160
Zero wait state
tWCU1
MEMW#/WR#/DOCW# inactive pulse
width
16
M
103
tWCU2
MEMW#/WR#/DOCW# inactive pulse
width
8M
163
tWCU3
IOW#/WR# inactive pulse width
8, 16
I/O
163
tRDYH
IOR#/MEMR#/RD#/DOCR#/IOW#/
MEMW#/WR#/DOCW# hold after
IOCHRDY RE
8, 16
M, I/O
120
tRDYA1
IOCHRDY valid after IOR#/MEMR#/
RD#/DOCR#/IOW#/MEMW#/WR#/
DOCW# FE
16
M, I/O
78