參數(shù)資料
型號: SC1189
廠商: Semtech Corporation
英文描述: Programmable synchronous DC/DC Converter, Dual LDO Controller
中文描述: 可編程同步DC / DC轉(zhuǎn)換器,雙LDO控制器
文件頁數(shù): 9/16頁
文件大?。?/td> 313K
代理商: SC1189
9
2004 Semtech Corp.
www.semtech.com
POWER MANAGEMENT
Component Selection
SC1189
SWITCHING SECTION
OUTPUT CAP
critical component. Because of fast transient load current
requirements in modern microprocessor core supplies, the
output capacitors must supply all transient load current
requirements until the current in the output inductor ramps
up to the new level. Output capacitor ESR is therefore one
of the most important criteria. The maximum ESR can be
simply calculated from:
CIT
ORS - Selection begins with the most
step
current
Transient
=
I
excursion
voltage
transient
Maximum
V
Where
=
I
V
R
t
t
t
t
ESR
For example, to meet a 100mV transient limit with a 10A
load step, the output capacitor ESR must be less than
10m
. To meet this kind of ESR level, there are three
available capacitor technologies.
y
g
o
n
h
c
e
T
.
a
C
h
c
a
E
.
Q
q
R
.
l
T
C
(
μ
)
F
R
S
m
(
)
E
C
(
μ
)
F
R
S
m
(
)
E
m
u
a
T
R
S
E
w
o
L
0
3
3
0
6
6
0
0
0
2
0
1
N
O
C
-
S
O
0
3
3
5
2
3
0
9
9
3
m
u
n
m
u
R
S
E
w
o
L
0
0
5
1
4
4
5
0
0
5
7
3
The choice of which to use is simply a cost/performance
issue, with Low ESR Aluminum being the cheapest, but
taking up the most space.
INDUCTOR
of output capacitor, the maximum allowable value of in-
ductor can be calculated. Too large an inductor will pro-
duce a slow current ramp rate and will cause the output
capacitor to supply more of the transient load current
for longer - leading to an output voltage sag below the
ESR excursion calculated above.
The maximum inductor value may be calculated from:
(
)
O
IN
O
A
A
t
ESR
I
V
V
or
V
of
lesser
the
is
V
where
V
C
R
L
The calculated maximum inductor value assumes 100%
and 0% duty cycle capability, so some allowance must be
made. Choosing an inductor value of 50 to 75% of the
calculated maximum will guarantee that the inductor cur-
rent will ramp fast enough to reduce the voltage dropped
across the ESR at a faster rate than the capacitor sags,
hence ensuring a good recovery from transient with no
additional excursions.
We must also be concerned with ripple current in the out-
put inductor and a general rule of thumb has been to
allow 10% of maximum output current as ripple current.
Note that most of the output voltage ripple is produced by
the inductor ripple current flowing in the output capacitor
ESR. Ripple current can be calculated from:
OSC
f
IN
L
L
4
V
I
RIPPLE
=
Ripple current allowance will define the minimum permit-
ted inductor value.
PO
WER FETS
criteria, with probably the most important being power
dissipation and power handling capability.
OP FET - The power dissipation in the top FET is a combi-
nation of conduction losses, switching losses and bottom
FET body diode recovery losses.
a) Conduction losses are simply calculated as:
IN
O
)
on
(
DS
2
O
COND
where
V
V
cycle
duty
δ
R
I
P
δ
=
b) Switching losses can be estimated by assuming a switch-
ing time, if we assume 100ns then:
2
IN
O
SW
10
V
I
P
or more generally,
=
4
f
)
t
t
V
I
P
OSC
f
r
IN
O
SW
+
=
c) Body diode recovery losses are more difficult to esti-
mate, but to a first approximation, it is reasonable to as-
sume that the stored charge on the bottom FET body di-
ode will be moved through the top FET as it starts to turn
on. The resulting power dissipation in the top FET will be:
f
V
Q
P
=
To a first order approximation, it is convenient to only con-
OSC
IN
RR
RR
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