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參數(shù)資料
| 型號(hào)： | SC1186CSW |
| 廠商： | Semtech Corporation |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection |
| 中文描述： | 無電容，NMOS管，150mA的低壓差穩(wěn)壓器的反向電流保護(hù) |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 109K |
| 代理商： | SC1186CSW |
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
1999 SEMTECH CORP.
PRELIMINARY - December 2, 1999
652 MITCHELL ROAD NEWBURY PARK CA 91320
SC1186
8
LAYOUT GUIDELINES
Careful attention to layout requirements are necessary
for successful implementation of the SC1186 PWM
controller. High currents switching at 140kHz are pre-
sent in the application and their effect on ground plane
voltage differentials must be understood and mini-
mized.
1). The high power parts of the circuit should be laid
out first. A ground plane should be used, the number
and position of ground plane interruptions should be
such as to not unnecessarily compromise ground plane
integrity. Isolated or semi-isolated areas of the ground
plane may be deliberately introduced to constrain
ground currents to particular areas, for example the
input capacitor and bottom FET ground.
2). The loop formed by the Input Capacitor(s) (Cin), the
Top FET (Q1) and the Bottom FET (Q2) must be kept
as small as possible. This loop contains all the high
current, fast transition switching. Connections should
be as wide and as short as possible to minimize loop
inductance. Minimizing this loop area will a) reduce
EMI, b) lower ground injection currents, resulting in
electrically “cleaner” grounds for the rest of the system
and c) minimize source ringing, resulting in more reli-
able gate switching signals.
3). The connection between the junction of Q1, Q2 and
the output inductor should be a wide trace or copper
region. It should be as short as practical. Since this
connection has fast voltage transitions, keeping this
connection short will minimize EMI. The connection
between the output inductor and the sense resistor
should be a wide trace or copper area, there are no
fast voltage or current transitions in this connection
and length is not so important, however adding unnec-
essary impedance will reduce efficiency.
Vout
12V IN
3.3V
Vo Lin1
Vo Lin2
5V
4uH
5mOhm
+
Cout
+
Cin
10
Q2
0.1uF
Q3
+
Cout Lin1
2.32k
Q4
+
Cout Lin2
1.00k
+
Cin Lin
SC1186
AGND
1
VCC
5
REF
6
LDOEN
7
CS-
8
CS+
9
PGNDH
10
DH
11
BSTH
15
EN
16
VOSENSE
17
VID4
18
VID3
19
VID2
20
VID1
21
VID0
22
DL
13
PGNDL
12
BSTL
14
GATE2
24
GATE1
2
LDOV
23
LDOS1
3
LDOS2
4
Q1
0.1uF
Heavy lines indicate
high current paths.
Layout diagram for the SC1186
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