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參數(shù)資料
| 型號(hào)： | SC1172 |
| 廠商： | Semtech Corporation |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection |
| 中文描述： | 無(wú)電容，NMOS管，150mA的低壓差穩(wěn)壓器的反向電流保護(hù) |
| 文件頁(yè)數(shù)： | 8/12頁(yè) |
| 文件大小： | 119K |
| 代理商： | SC1172 |
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER WITH LOW DROPOUT
REGULATOR CONTROLLER
SC1172/3
1999 SEMTECH CORP.
October 25, 1999
652 MITCHELL ROAD NEWBURY PARK CA 91320
8
LAYOUT GUIDELINES
Careful attention to layout requirements are necessary
for successful implementation of the SC1172/3 PWM
controller. High currents switching at 200kHz are pre-
sent in the application and their effect on ground plane
voltage differentials must be understood and mini-
mized.
1). The high power parts of the circuit should be laid out
first. A ground plane should be used, the number and
position of ground plane interruptions should be such
as to not unnecessarily compromise ground plane in-
tegrity. Isolated or semi-isolated areas of the ground
plane may be deliberately introduced to constrain
ground currents to particular areas, for example the in-
put capacitor and bottom FET ground.
2). The loop formed by the Input Capacitor(s) (Cin), the
Top FET (Q1) and the Bottom FET (Q2) must be kept
as small as possible. This loop contains all the high cur-
rent, fast transition switching. Connections should be as
wide and as short as possible to minimize loop induc-
tance. Minimizing this loop area will a) reduce EMI, b)
lower ground injection currents, resulting in electrically
“cleaner” grounds for the rest of the system and c) mini-
mize source ringing, resulting in more reliable gate
switching signals.
3). The connection between the junction of Q1, Q2 and
the output inductor should be a wide trace or copper
region. It should be as short as practical. Since this
connection has fast voltage transitions, keeping this
connection short will minimize EMI. The connection be-
tween the output inductor and the sense resistor should
be a wide trace or copper area, there are no fast volt-
age or current transitions in this connection and length
is not so important, however adding unnecessary
impedance will reduce efficiency.
Vout
12V IN
5V
Vo Lin
5V
4uH
5mOhm
+
Cout
+
Cin
10
Q2
0.1uF
Q3
+
Cout Lin
2.32k
1.00k
RB
RA
+
Cin Lin
SC1172/3
AGND
1
VCC
5
OVP
6
PWRGOOD
7
CS-
8
CS+
9
PGNDH
10
DH
11
BSTH
15
EN
16
VO SENSE
17
VID4
18
VID3
19
VID2
20
VID1
21
VID0
22
DL
13
PGNDL
12
BSTL
14
NC
24
GATE
2
LDOV
23
LDOS
3
NC
4
Q1
0.1uF
Heavy lines indicate
high current paths.
are not required. LDOS connects to
Vo Lin
For SC1172, RA and RB
Layout diagram for the SC1172/3
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| SC1172CSW | 制造商:Semtech Corporation 功能描述: |
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