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參數(shù)資料
| 型號： | SC1152CS |
| 廠商： | Semtech Corporation |
| 英文描述： | PROGRAMMABLE SYNCHRONOUS DC/DC CONTROLLER FOR ADVANCED PROCESSORS |
| 中文描述： | 可編程同步DC / DC控制器的先進的處理器 |
| 文件頁數(shù)： | 5/7頁 |
| 文件大小： | 77K |
| 代理商： | SC1152CS |
SC1152
PROGRAMMABLE SYNCHRONOUS DC/DC
CONTROLLER FOR ADVANCED PROCESSORS
1998 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
April 28, 1998
OUTPUT VOLTAGE TABLE
5
NOTE:
(1) All VID codes not specifically listed are invalid and cause shutdown exactly as if the shutdown pin had been
asserted.
Unless specified: V
CC
= 4.75V to 5.25V; GND = PGND = 0V; FB = V
O
; 0mV < (CS(+) - CS(-)) < 60mV; T
J
= 25°C
PARAMETER
CONDITIONS
VID
43210
00101
00100
00011
00010
00001
00000
11111
11110
11101
11100
11011
11010
11001
11000
10111
10110
10101
10100
10011
10010
10001
10000
MIN
TYP
MAX
UNITS
Output Voltage
(1)
I
O
= 2A in Application Circuit
(Figure 1)
1.782
1.832
1.881
1.931
1.980
2.030
1.980
2.079
2.178
2.277
2.376
2.475
2.574
2.673
2.772
2.871
2.970
3.069
3.168
3.267
3.366
3.465
1.800
1.850
1.900
1.950
2.000
2.050
2.000
2.100
2.200
2.300
2.400
2.500
2.600
2.700
2.800
2.900
3.000
3.100
3.200
3.300
3.400
3.500
1.818
1.868
1.919
1.969
2.020
2.070
2.020
2.121
2.222
2.323
2.424
2.525
2.626
2.727
2.828
2.929
3.030
3.131
3.232
3.333
3.434
3.535
V
THEORY OF OPERATION
The voltage at the V
OSENSE
pin is applied, through the internal precision resistor feedback chain, to the inverting
input of the error amplifier. The non-inverting input of the error amplifier is supplied with a DC voltage derived by
the DAC from the internal trimmed bandgap voltage reference. The output of the error amplifier is compared to
the triangular output of the internal oscillator to generate a fixed frequency, variable duty cycle pulse train. The
internal oscillator uses an on-chip capacitor and precision trimmed current sources to set the frequency to 200
kHz.
The generated pulse train is gated with the output of the current limit latch and the inhibit signal to produce a
drive signal for the upper FET. It is also inverted to produce a drive signal for the lower FET. These FET drive
signals are modified by the “shoot-through control” circuitry so that the top FET turn-on is delayed until the bottom
FET has turned off, and visa-versa.
The current limit latch is set (ending the upper FET drive pulse early) if the current limit comparator indicates an
overcurrent condition. The latch is reset at the start of each oscillator period.
The PWRGOOD and OVP signals are derived from the voltage at the V
OSENSE
pin by comparators fed from the
internal feedback chain.
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