
Chapter 23 Analog-to-Digital Converter (S12ATD10B8CV3)
MC9S12XDP512 Data Sheet, Rev. 2.12
858
Freescale Semiconductor
ATDDR3L
10-BIT
BIT 1
U
BIT 0
U
0
8-BIT
W
ATDDR4H
10-BIT BIT 9 MSB
BIT 7 MSB
BIT 8
BIT 6
BIT 7
BIT 5
BIT 6
BIT 4
BIT 5
BIT 3
BIT 4
BIT 2
BIT 3
BIT 1
BIT 2
BIT 0
8-BIT
W
ATDDR4L
10-BIT
BIT 1
U
BIT 0
U
0
8-BIT
W
ATDD45H
10-BIT BIT 9 MSB
BIT 7 MSB
BIT 8
BIT 6
BIT 7
BIT 5
BIT 6
BIT 4
BIT 5
BIT 3
BIT 4
BIT 2
BIT 3
BIT 1
BIT 2
BIT 0
8-BIT
W
ATDD45L
10-BIT
BIT 1
U
BIT 0
U
0
8-BIT
W
ATDD46H
10-BIT BIT 9 MSB
BIT 7 MSB
BIT 8
BIT 6
BIT 7
BIT 5
BIT 6
BIT 4
BIT 5
BIT 3
BIT 4
BIT 2
BIT 3
BIT 1
BIT 2
BIT 0
8-BIT
W
ATDDR6L
10-BIT
BIT 1
U
BIT 0
U
0
8-BIT
W
ATDD47H
10-BIT BIT 9 MSB
BIT 7 MSB
BIT 8
BIT 6
BIT 7
BIT 5
BIT 6
BIT 4
BIT 5
BIT 3
BIT 4
BIT 2
BIT 3
BIT 1
BIT 2
BIT 0
8-BIT
W
ATDD47L
10-BIT
BIT 1
U
BIT 0
U
0
8-BIT
W
Right Justied Result Data
Note: The read portion of the right justied result data registers has been divided to show the bit position when reading 10-bit
ATDDR0H
10-BIT
0
BIT 9 MSB
0
BIT 8
0
8-BIT
W
ATDDR0L
10-BIT
BIT 7
BIT 7 MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
8-BIT
W
Register
Name
Bit 7
654321
Bit 0
= Unimplemented or Reserved
Figure 23-2. ATD Register Summary (Sheet 3 of 5)