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參數資料
| 型號： | SBDIP |
| 廠商： | Intersil Corporation |
| 英文描述： | High-Reliability CMOS 8-Bit Microprocessor |
| 中文描述： | 高可靠性的CMOS 8位微處理器 |
| 文件頁數： | 6/8頁 |
| 文件大?。?/td> | 44K |
| 代理商： | SBDIP |
3-35
NOTES:
6. This timing diagram is used to show signal relationships only, and does not represent any specific machine cycle.
7. All measurements are referenced to 50% point of the waveforms.
8. Shaded areas indicate “don’t care” or undefined state. Multiple transitions may occur during this period.
FIGURE 2. TIMING WAVEFORMS
0
2
3
4
5
6
7
0
00
10
20
30
40
50
60
70
00
01
11
21
31
41
51
61
71
01
t
W
CLOCK
t
PLH
t
PHL
TPA
TPB
t
SU
t
H
t
PLH
t
PHL
t
PLH,
t
P
H
L
LOW ORDER
ADDRESS BYTE
MEMORY
ADDRESS
t
PLH
MRD
(MEMORY
READ CYCLE)
t
PHL
t
PLH
t
PLH
t
PHL
t
PHL
MWR
(MEMORY
WRITE CYCLE)
DATA FROM
CPU TO BUS
STATE
CODES
t
PLH
t
PHL
t
PLH
t
PHL
Q
t
PLH,
t
PHL
N0, N1, N2
(I/O
EXECUTION
CYCLE)
t
PLH
DATA
LATCHED IN CPU
DATA FROM
BUS TO CPU
t
H
DMA
INTERRUPT
SAMPLED (S1, S2)
t
SU
t
H
t
SU
t
H
DMA
REQUEST
INTERRUPT
REQUEST
FLAG LINES
SAMPLED (IN SI)
EF 1-4
t
SU
t
H
WAIT
CLEAR
t
W
t
SU
ANY NEGATIVE
TRANSITION
t
PLH,
t
PHL
t
PLH
t
PHL
SAMPLED (S1, S2, S3)
t
SU
1
HIGH ORDER
ADDRESS BYTE
t
PLH,
t
PHL
t
PLH,
t
P
H
L
CDP1802AC/3
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