參數(shù)資料
型號(hào): SAK-XC2388C-104F80L
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP144
封裝: 0.50 MM PITCH, GREEN, PLASTIC, LQFP-144
文件頁數(shù): 30/147頁
文件大?。?/td> 1798K
代理商: SAK-XC2388C-104F80L
XC2387C, XC2388C
XC2000 Family Derivatives / High Line
Electrical Parameters
Data Sheet
125
V1.2, 2010-09
Table 33 is valid under the following conditions:
C
L= 20 pF; voltage_range= lower ;
voltage_range= lower
Address output valid delay
for AD15 ... AD0 (MUX
mode)
t
13 CC
815
ns
Output valid delay for CS
t
14 CC
713
ns
Data output valid delay for
AD15 ... AD0 (write data,
MUX mode)
t
15 CC
815
ns
Data output valid delay for
D15 ... D0 (write data,
DEMUX mode)
t
16 CC
815
ns
Output hold time for RD,
WR(L/H)
t
20 CC
-2
6
8
ns
Output hold time for BHE,
ALE
t
21 CC
-2
6
10
ns
Address output hold time
for AD15 ... AD0
t
23 CC
-3
6
8
ns
Output hold time for CS
t
24 CC
-3
6
11
ns
Data output hold time for
D15 ... D0 and AD15 ...
AD0
t
25 CC
-3
6
8
ns
Input setup time for
READY, D15 ... D0, AD15
... AD0
t
30 SR
25
15
ns
Input hold time READY,
D15 ... D0, AD15 ... AD0
1)
t
31 SR
0
-7
ns
1) Read data are latched with the same internal clock edge that triggers the address change and the rising edge
of RD. Address changes before the end of RD have no impact on (demultiplexed) read cycles. Read data can
change after the rising edge of RD.
Table 32
External Bus Timing for Upper Voltage Range (cont’d)
Parameter
Symbol
Values
Unit
Note /
Test Condition
Min.
Typ.
Max.
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