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參數(shù)資料
| 型號： | SAK-C167SR-LM |
| 廠商： | SIEMENS A G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-Bit CMOS Single-Chip Microcontroller |
| 中文描述： | MICROCONTROLLER, MQFP144 |
| 文件頁數(shù)： | 60/80頁 |
| 文件大小： | 1151K |
| 代理商： | SAK-C167SR-LM |
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C167CS-4R
C167CS-L
Data Sheet
56
V2.0, 2000-06
P0.15-13 (P0H.7-5). Register RP0H can be loaded from the upper half of register
RSTCON under software control.
Table 10
associates the combinations of these three bits with the respective clock
generation mode.
Prescaler Operation
When prescaler operation is configured (CLKCFG=001
B
) the CPU clock is derived from
the internal oscillator (input clock signal) by a 2:1 prescaler.
The frequency of
f
CPU
is half the frequency of
f
OSC
and the high and low time of
f
CPU
(i.e.
the duration of an individual TCL) is defined by the period of the input clock
f
OSC
.
The timings listed in the AC Characteristics that refer to TCLs therefore can be
calculated using the period of
f
OSC
for any TCL.
Phase Locked Loop
When PLL operation is configured (via CLKCFG) the on-chip phase locked loop is
enabled and provides the CPU clock (see table above). The PLL multiplies the input
frequency by the factor
F
which is selected via the combination of pins P0.15-13 (i.e.
f
CPU
=
f
OSC
×
F
). With every
F
’th transition of
f
OSC
the PLL circuit synchronizes the CPU
clock to the input clock. This synchronization is done smoothly, i.e. the CPU clock
frequency does not change abruptly.
Due to this adaptation to the input clock the frequency of
f
CPU
is constantly adjusted so
it is locked to
f
OSC
. The slight variation causes a jitter of
f
CPU
which also effects the
duration of individual TCLs.
Table 10
CLKCFG
(RP0H.7-5)
1 1 1
1 1 0
1 0 1
1 0 0
0 1 1
0 1 0
0 0 1
0 0 0
C167CS Clock Generation Modes
CPU Frequency
f
CPU
=
f
OSC
×
F
f
OSC
×
4
f
OSC
×
3
f
OSC
×
2
f
OSC
×
5
f
OSC
×
1
f
OSC
×
1.5
f
OSC
/ 2
f
OSC
×
2.5
External Clock
Input Range
1)
2.5 to 8.25 MHz
3.33 to 11 MHz
5 to 16.5 MHz
2 to 6.6 MHz
1 to 33 MHz
6.66 to 22 MHz
2 to 66 MHz
4 to 13.2 MHz
1)
The external clock input range refers to a CPU clock range of 10 … 33 MHz.
2)
The maximum frequency depends on the duty cycle of the external clock signal.
Notes
Default configuration
–
–
–
Direct drive
2)
–
CPU clock via prescaler
–
相關(guān)PDF資料 |
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| SAB-C167CR-LM | 16-Bit CMOS Single-Chip Microcontroller |
| SAB-C167SR-LM | 16-Bit CMOS Single-Chip Microcontroller |
| SAK-C505L | 8-bit CMOS Microcontroller |
| SAF-C505L-4EM | 8-bit CMOS Microcontroller |
| SAB-C505 | 8-bit CMOS Microcontroller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAK-C167SR-LM HA+ | 功能描述:16位微控制器 - MCU MICROCONTROLLER 16-BIT RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數(shù)據(jù)總線寬度:16 bit 最大時鐘頻率:24 MHz 程序存儲器大小:8 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風(fēng)格:SMD/SMT |
| SAK-C167SR-LM HA+ TR | 制造商:Infineon Technologies AG 功能描述: |
| SAK-C167SR-LMHA+ | 制造商:Infineon Technologies AG 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
| SAKC167SRLMHA+X | 制造商:Infineon Technologies AG 功能描述:MCU 16-Bit C166 CISC/RISC ROMLess 5V 144-Pin MQFP |
| SAKC167SRLMHA+XT | 制造商:Infineon Technologies AG 功能描述:MCU 16-Bit C166 CISC/RISC ROMLess 5V 144-Pin MQFP |
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