參數(shù)資料
型號(hào): SAK-C164CI-8EMCB
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 16-BIT, OTPROM, 20 MHz, MICROCONTROLLER, PQFP80
封裝: 0.65 MM PITCH, METRIC, PLASTIC, QFP-80
文件頁(yè)數(shù): 69/80頁(yè)
文件大?。?/td> 1337K
代理商: SAK-C164CI-8EMCB
C164CI/SI
C164CL/SL
Data Sheet
66
V2.0, 2001-05
Data valid to WR
t22 CC 20 + tC
2TCL - 20
+
tC
ns
Data hold after WR
t24 CC 10 + tF
TCL - 10
+
tF
ns
ALE rising edge after RD,
WR
t26 CC -10 + tF
-10 +
tF
ns
Address hold after WR2)
t28 CC 0 + tF
0 +
tF
ns
ALE falling edge to CS3)
t38 CC -4 - tA
10 -
tA
-4 -
tA
10 -
tA
ns
CS low to Valid Data In3)
t39 SR –
40 +
tC + 2tA
3TCL - 20
+
tC + 2tA
ns
CS hold after RD, WR3)
t41 CC 6 + tF
TCL - 14
+
tF
ns
ALE falling edge to RdCS,
WrCS (with RW-delay)
t42 CC 16 + tA
TCL - 4
+
tA
ns
ALE falling edge to RdCS,
WrCS (no RW-delay)
t43 CC -4 + tA
-4
+
tA
ns
RdCS to Valid Data In
(with RW-delay)
t46 SR –
16 +
tC
2TCL - 24
+
tC
ns
RdCS to Valid Data In
(no RW-delay)
t47 SR –
36 +
tC
3TCL - 24
+
tC
ns
RdCS, WrCS Low Time
(with RW-delay)
t48 CC 30 + tC
2TCL - 10
+
tC
ns
RdCS, WrCS Low Time
(no RW-delay)
t49 CC 50 + tC
3TCL - 10
+
tC
ns
Data valid to WrCS
t50 CC 26 + tC
2TCL - 14
+
tC
ns
Data hold after RdCS
t51 SR 0
0
ns
Data float after RdCS
(with RW-delay)1)
t53 SR –
20 +
tF
2TCL - 20
+ 2
tA + tF
ns
Demultiplexed Bus (cont’d)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2
tA + tC + tF (80 ns at 25 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock
= 25 MHz
Variable CPU Clock
1 / 2TCL = 1 to 25 MHz
Unit
min.
max.
min.
max.
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