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| 型號(hào)： | SAH-XC2387C-104F100L |
| 廠(chǎng)商： | INFINEON TECHNOLOGIES AG |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP144 |
| 封裝： | 0.50 MM PITCH, GREEN, PLASTIC, LQFP-144 |
| 文件頁(yè)數(shù)： | 17/147頁(yè) |
| 文件大?。?/td> | 1798K |
| 代理商： | SAH-XC2387C-104F100L |
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XC2387C, XC2388C
XC2000 Family Derivatives / High Line
Electrical Parameters
Data Sheet
113
V1.2, 2010-09
The timing in the AC Characteristics refers to TCSs. Timing must be calculated using the
minimum TCS possible under the given circumstances.
The actual minimum value for TCS depends on the jitter of the PLL. Because the PLL is
constantly adjusting its output frequency to correspond to the input frequency (from
crystal or oscillator), the accumulated jitter is limited. This means that the relative
deviation for periods of more than one TCS is lower than for a single TCS (see formulas
and Figure 20).
This is especially important for bus cycles using waitstates and for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is negligible.
The value of the accumulated PLL jitter depends on the number of consecutive VCO
output cycles within the respective timeframe. The VCO output clock is divided by the
output prescaler K2 to generate the system clock signal
f
SYS. The number of VCO cycles
is K2
× T, where T is the number of consecutive f
SYS cycles (TCS).
The maximum accumulated jitter (long-term jitter) D
Tmax is defined by:
D
Tmax [ns] = ±(220 / (K2 × fSYS) + 4.3)
This maximum value is applicable, if either the number of clock cycles T > (
f
SYS / 1.2) or
the prescaler value K2 > 17.
In all other cases for a timeframe of T
× TCS the accumulated jitter D
T is determined by:
D
T [ns] = DTmax × [(1 - 0.058 × K2) × (T - 1) / (0.83 × fSYS - 1) + 0.058 × K2]
f
SYS in [MHz] in all formulas.
Example, for a period of 3 TCSs @ 33 MHz and K2 = 4:
D
max = ±(220 / (4 × 33) + 4.3) = 5.97 ns (Not applicable directly in this case!)
D
3 = 5.97 × [(1 - 0.058 × 4) × (3 - 1) / (0.83 × 33 - 1) + 0.058 × 4]
= 5.97
× [0.768 × 2 / 26.39 + 0.232]
= 1.7 ns
Example, for a period of 3 TCSs @ 33 MHz and K2 = 2:
D
max = ±(220 / (2 × 33) + 4.3) = 7.63 ns (Not applicable directly in this case!)
D
3 = 7.63 × [(1 - 0.058 × 2) × (3 - 1) / (0.83 × 33 - 1) + 0.058 × 2]
= 7.63
× [0.884 × 2 / 26.39 + 0.116]
= 1.4 ns
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