參數(shù)資料
型號: SAF7129AH
廠商: NXP Semiconductors N.V.
元件分類: 通用總線功能
英文描述: Digital video encoder
文件頁數(shù): 22/56頁
文件大小: 259K
代理商: SAF7129AH
2004 Mar 16
22
Philips Semiconductors
Product specification
Digital video encoder
SAF7129AH
Table 22
Subaddress 51H
Table 23
Subaddress 52H
Table 24
Subaddress 53H
Table 25
Subaddress 54H
BIT
SYMBOL
DESCRIPTION
7 to 0
LUTU[7:0]
LUT for the colour values inserted in case of key colour 2 U detection in the MPEG input
data stream.
LUTU[7:0] = 80H; default value after reset
BIT
SYMBOL
DESCRIPTION
7 to 0
LUTV[7:0]
LUT for the colour values inserted in case of key colour 2 V detection in the MPEG input
data stream.
LUTV[7:0] = 80H; default value after reset
BIT
SYMBOL
DESCRIPTION
7 to 0
LUTY[7:0]
LUT for the colour values inserted in case of key colour 2 Y detection in the MPEG input
data stream.
LUTY[7:0] = 80H; default value after reset
BIT
SYMBOL
DESCRIPTION
7
VPSEN
0 = video programming system data insertion is disabled; default state after reset
1 = video programming system data insertion in line 16 is enabled
This bit is not used and should be set to logic 0.
0 = encoder path is fed with MP
B
input data; fader is bypassed; default state after reset
1 = encoder path is fed with output signal of fader; see Section 7.1
0 = RGB path is fed with MP
B
input data; fader is bypassed; default state after reset
1 = RGB path is fed with output signal of fader; see Section 7.1
0 = not supported in current version; do not use
1 = recommended value; default state after reset
0 = not supported in current version; do not use
1 = recommended value; default state after reset
0 = MP
B
data is sampled on the rising clock edge; default state after reset
1 = MP
B
data is sampled on the falling clock edge
0 = MP
A
data is sampled on the rising clock edge; default state after reset
1 = MP
A
data is sampled on the falling clock edge
6
5
ENCIN
4
RGBIN
3
DELIN
2
VPSEL
1
EDGE2
0
EDGE1
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