參數(shù)資料
型號: SAF-XC164CS-8F40F
廠商: INFINEON TECHNOLOGIES AG
英文描述: 16-Bit Single-Chip Microcontroller
中文描述: 16位單片機
文件頁數(shù): 60/71頁
文件大?。?/td> 2661K
代理商: SAF-XC164CS-8F40F
XC164
Derivatives
Timing Parameters
Data Sheet
56
V2.1, 2003-06
5
Timing Parameters
5.1
Definition of Internal Timing
The internal operation of the XC164 is controlled by the internal master clock
f
MC
.
The master clock signal
f
MC
can be generated from the oscillator clock signal
f
OSC
via
different mechanisms. The duration of master clock periods (TCMs) and their variation
(and also the derived external timing) depend on the used mechanism to generate
f
MC
.
This influence must be regarded when calculating the timings for the XC164.
Figure 15
Generation Mechanisms for the Master Clock
Note: The example for PLL operation shown in
Figure 15
refers to a PLL factor of 1:4,
the example for prescaler operation refers to a divider factor of 2:1.
The used mechanism to generate the master clock is selected by register PLLCON.
CPU and EBC are clocked with the CPU clock signal
f
CPU
. The CPU clock can have the
same frequency as the master clock (
f
CPU
=
f
MC
) or can be the master clock divided by
two:
f
CPU
=
f
MC
/ 2. This factor is selected by bit CPSYS in register SYSCON1.
The specification of the external timing (AC Characteristics) depends on the period of the
CPU clock, called “TCP”.
The other peripherals are supplied with the system clock signal
f
SYS
which has the same
frequency as the CPU clock signal
f
CPU
.
TCM
TCM
f
MC
f
OSC
f
MC
f
OSC
Phase Locked Loop Operation (1:N)
Direct Clock Drive (1:1)
TCM
f
MC
f
OSC
Prescaler Operation (N:1)
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