參數(shù)資料
型號: SAF-XC164CS-16R40F
廠商: INFINEON TECHNOLOGIES AG
英文描述: 16-Bit Single-Chip Microcontroller
中文描述: 16位單片機(jī)
文件頁數(shù): 67/71頁
文件大小: 2661K
代理商: SAF-XC164CS-16R40F
XC164
Derivatives
Timing Parameters
Data Sheet
63
V2.1, 2003-06
Note: The shaded parameters have been verified by characterization.
They are not 100% tested.
Table 19
Parameter
External Bus Cycle Timing
(Operating Conditions apply)
Symbol
Limits
Unit
min.
max.
13
Output valid delay for:
RD, WR(L/H)
Output valid delay for:
A23
A16, BHE, ALE
Output valid delay for:
A15
A0 (on PORT1)
Output valid delay for:
A15
A0 (on PORT0)
Output valid delay for:
CS
Output valid delay for:
D15
D0 (write data, mux-mode)
Output valid delay for:
D15
D0 (write data, demux-mode)
Output hold time for:
RD, WR(L/H)
Output hold time for:
A23
A16, BHE, ALE
Output hold time for:
A15
A0 (on PORT0)
Output hold time for:
CS
Output hold time for:
D15
D0 (write data)
Input setup time for:
READY, D15
D0 (read data)
Input hold time
READY, D15
D0 (read data)
1)
tc
10
CC 1
ns
tc
11
CC -1
7
ns
tc
12
CC 1
16
ns
tc
13
CC 3
16
ns
tc
14
CC 1
14
ns
tc
15
CC 3
17
ns
tc
16
CC 3
17
ns
tc
20
CC -3
3
ns
tc
21
CC 0
8
ns
tc
23
CC 1
13
ns
tc
24
CC -3
3
ns
tc
25
CC 1
13
ns
tc
30
SR 24
ns
tc
31
SR -5
ns
1)
Read data are latched with the same (internal) clock edge that triggers the address change and the rising edge
of RD. Therefore address changes before the end of RD have no impact on (demultiplexed) read cycles. Read
data can be removed after the rising edge of RD.
相關(guān)PDF資料
PDF描述
SAF-XC164CS-8F20F 16-Bit Single-Chip Microcontroller
SAK-XC164CS-8F40F 16-Bit Single-Chip Microcontroller
SAF-XC164CS-8F40F 16-Bit Single-Chip Microcontroller
SAF-XC164CS-8R20F 16-Bit Single-Chip Microcontroller
SAF-XC164CS-8R40F 16-Bit Single-Chip Microcontroller
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