
TC11IB
Data Sheet
28
V2.4, 2004-06
High-Speed Synchronous Serial Interface
Figure 6 shows a global view of the functional blocks of the High-Speed Synchronous
Serial interface SSC.
Figure 6
General Block Diagram of the SSC Interfaces
The SSC Module has three I/O lines, located at Port 1. The SSC Module is further
supplied by separate clock control, interrupt control, address decoding, and port control
logic.
The SSC supports full-duplex and half-duplex serial synchronous communication up to
24 MBaud (@ 48 MHz module clock). The serial clock signal can be generated by the
SSC itself (master mode) or can be received from an external master (slave mode). Data
width, shift direction, clock polarity, and phase are programmable. This allows
communication with SPI-compatible devices. Transmission and reception of data are
double-buffered. A 16-bit baud rate generator provides the SSC with a separate serial
clock signal.
M C B 0 4 952
Clo c k
C ontro l
Ad d re s s
D e c ode r
In te rru p t
C ontro l
f
SS C
SSC
Mo d u le
Po rt
Co n tro l
P 1 .2 / M T S R
Tx D
Rx D
Tx D
Rx D
Ma s te r
Sla v e
Slav
e
S
C
LK
M
a
st
er
P 1 .1 / M R S T
P 1 .0 / S C L K