參數(shù)資料
型號： SAF-C164SV-2R25F
廠商： INFINEON TECHNOLOGIES AG
英文描述： 16-Bit Single-Chip Microcontroller
中文描述： 16位單片機
文件頁數(shù)： 51/65頁
文件大?。?/td> 648K
代理商： SAF-C164SV-2R25F
C164SV
Data Sheet
47
V1.0, 2003-04
Preliminary
Due to this adaptation to the input clock the frequency of
f
CPU
is constantly adjusted so
it is locked to
f
OSC
. The slight variation causes a jitter of
f
CPU
which also effects the
duration of individual TCLs.
The timings listed in the AC Characteristics that refer to TCLs therefore must be
calculated using the minimum TCL that is possible under the respective circumstances.
The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is
constantly adjusting its output frequency so it corresponds to the applied input frequency
(crystal or oscillator) the relative deviation for periods of more than one TCL is lower than
for one single TCL (see formula and
Figure 11
).
For a period of
N
×
TCL the minimum value is computed using the corresponding
deviation D
N
:
(
N
×
TCL)
min
=
N
×
TCL
NOM
- D
N
; D
N
[ns] =
±
(13.3 +
N
×
6.3)/
f
CPU
[MHz],
where
N
= number of consecutive TCLs and 1
≤
N
≤
40.
So for a period of 3 TCLs @ 25 MHz (i.e.
N
= 3): D
3
= (13.3 +
3
×
6.3)/25 = 1.288 ns,
and (3TCL)
min
= 3TCL
NOM
- 1.288 ns = 58.7 ns (@
f
CPU
= 25 MHz).
This is especially important for bus cycles using waitstates and e.g. for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is neglectible.
Note: For all periods longer than 40 TCL the N = 40 value can be used (see
Figure 11
).
Figure 11
Approximated Maximum Accumulated PLL Jitter
MCD04455
N
Max. jitter
D
N
±1
±10
±20
±30
ns
±26.5
1
10
20
40
This approximated formula is valid for
1
N
<
f
CPU
<
10 MHz
16 MHz
20 MHz
25 MHz
30
<
<
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