
1997 Intermediate Version
Semiconductor Group
22
1997-10-01
C163-16F
Flash Memory Overview
The on-chip Flash module of the C163-16F has a capacity of 128 KByte and combines the
advantages of a very fast read access of 32 bit in one machine cycle with protected but simple
writing algorithms for programming and erase. Read accesses of code and data are possible in any
addressing mode, thus realizing the highest CPU performance with fetch of double word
instructions in a single cycle. Based on the Flash cell concept (split gate) special algorithms for over/
under-programming or erase, with verify operations, are not necessary. For optimized programming
efficiency, a burst (paging) mode is offered which allows to load up to 64 Bytes into an assembly
buffer with normal CPU timing before this buffer is stored into the Flash with a write command. The
algorithms for the program and erase operations are automatically controlled by the internal
command state machine.
Note: Erased Flash memory cells contain all ‘0’s, contrary to standard EPROMs.
The C163-16F Flash module is a 1 Mbit, 5 Volt-only Flash memory organized as 32K Doublewords
of 32 bit each. The physical structure of the Flash array allows simultaneous access to 64 Byte for
write operations.
The lower 32 KBytes of the on-chip Flash memory of the C163-16F can be mapped to either
segment 0 (00’0000H to 00’7FFFH) or segment 1 (01’0000H to 01’7FFFH) during the initialization
phase to allow external memory to be used for additional system flexibility. The upper 96 KBytes of
the on-chip Flash memory are assigned to locations 01’8000H to 02’FFFFH.
Figure 7
Mapping of the On-chip Flash Module Sectors
2
1
0
02’FFFFH
02’0000
01’8000
00’0000
H
01’0000 H
0
1
3
2
64 - 128 K
32 - 64 K
0 - 32 K
01’FFFFH
01’0000 H
00’0000 H
00’8000 H
Physical Flash
Address
Mapping
MCS03668
Memory Segments
Physical Flash Space