參數(shù)資料
型號(hào)： SAA7283ZP
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： Terrestrial Digital Sound Decoder TDSD3
中文描述： SPECIALTY CONSUMER CIRCUIT, PDIP52
封裝： 0.600 INCH, PLASTIC, SOT-247-1, SDIP-52
文件頁(yè)數(shù)： 9/36頁(yè)
文件大?。?/td> 178K
代理商： SAA7283ZP
1996 Oct 24
9
Philips Semiconductors
Preliminary specification
Terrestrial Digital Sound Decoder (TDSD3)
SAA7283
FUNCTIONAL DESCRIPTION
DQPSK demodulation
Q
UADRATURE MIXERS
,
BASEBAND FILTERS AND AUTOMATIC
GAIN CONTROL
(AGC)
The DQPSK signal is fed into two differential input mixers,
where it is mixed with quadrature phases generated by the
carrier-loop quadrature VCO. The quadrature signals
modulated onto the NICAM carrier are thus recovered.
The mixers can be driven by either a single-ended or
differential source. In single-ended mode, the device is
driven directly from the sound IF down-converter into the
DQPSK input pin, with the MIXREF pin decoupled.
In differential mode, the signal is applied between the
DQPSK and MIXREF pins.
The outputs from the mixers are then fed into a
pulse-shaping filter, and FM/vision filter stage which filters
out all interference components, including AM carrier for
French NICAM L system. The signal from the filtering
stages is then fed into the AGC, which ensures that the
phase comparator gain remains constant, irrespective of
the input signal level. This is important to maintain the
stability of Costas loop PLL.
AGC
CONTROLLER
The AGC controller monitors the I and Q channel signals
at the input to the carrier loop-phase comparator and
generates a reference voltage to set the AGC output level.
E
YE BUFFER
A differential to the single-ended converter provides the
baseband signal as an output at the pins CEYE and SEYE
for the I and Q channels respectively for eye-height
monitoring.
B
IT RATE CLOCK RECOVERY
The I and Q channels are processed using edge detectors
and monostables, which generate a signal with a coherent
component at the data symbol rate. The outputs from the
I and Q channel monostables are each compared with the
clock derived from PCLK (364 kHz nominal), the resultant
output is used to derive a 3-state control signal used to
control two current sources at the CLKLPF output.
This error signal is loop filtered and used to control the
master clock oscillator. The bit rate clock, PCLK, and
symbol clock are derived from the master clock.
NICAM 728 decoding
D
ECODING FUNCTIONS
The device performs all decoding functions in accordance
with the EBU NICAM 728 specification. After locking to the
frame alignment word, the data is de-scrambled by
application of the defined pseudo random binary
sequence, and the device synchronizes to the periodic
frame flag bit C0.
The relevant control information and scale factor word is
extracted, and with the integrated RAM the data is
de-interleaved and the scale factor word is extracted, and
expanded to 14 bits. Parity checking on the eleventh bit of
each sample word is carried out to reveal any sound
sample errors, which if detected are flagged, with the last
good sample being held.
Automatic muting
Enable when AMDIS = LOW. The I
2
C-bus section has two
registers which define an upper and lower limit for the
automatic muting function. When the number of errors
within a 128 ms period exceeds the number stored in the
upper error limit register, then the automatic muting will
switch the device output to the FM input, (dependent on
the relevant control bits in the I
2
C-bus) and mute
(set to zero) the data input to the filter (in that order).
When the error count in a 128 ms period is less than the
value stored in the lower error limit register then the data
into the filter is uninterrupted, and the device output is
switched back to the DAC (dependent on the value of the
relevant control bits in the I
2
C-bus). During the muting
operation the open-drain pin MUTE is pulled LOW and the
AM bit in the status-byte is set HIGH. Figure 4 shows the
dependency of the automatic muting function on
error_count, RSSF, C4OV, output state and application
mode. The automatic muting function, if enabled, will
override user mute via the MUTE pin/bit.
When the transmission is DATA format or currently
undefined format (C3 = logic 1) the device will
automatically switch to the FM inputs regardless of
RSSF/C4OV states, and whether the automatic muting
function AMDIS is enabled or disabled.
相關(guān)PDF資料
PDF描述
SAA7283 Terrestrial Digital Sound Decoder TDSD3
SAA7283GP Terrestrial Digital Sound Decoder TDSD3
SAA7284GP Terrestrial digital sound decoder for conventional intercarrier PLL-IF systems
SAA7384 Terrestrial digital sound decoder for conventional intercarrier PLL-IF systems
SAA7284 Terrestrial digital sound decoder for conventional intercarrier PLL-IF systems
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參數(shù)描述
SAA7284 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Terrestrial digital sound decoder for conventional intercarrier PLL-IF systems
SAA7284GP 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Terrestrial digital sound decoder for conventional intercarrier PLL-IF systems
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