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參數(shù)資料
| 型號： | SAA7221HS |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Integrated MPEG AVGD decoders |
| 中文描述： | 集成的MPEG解碼器AVGD |
| 文件頁數(shù)： | 13/28頁 |
| 文件大?。?/td> | 101K |
| 代理商： | SAA7221HS |
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2000 Jan 31
13
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
SAA7215; SAA7216; SAA7221
AV_DATA(7)
ERROR
A_STROBE
V_STROBE
V
SS
(gate input)
CPU_SEL(0)
CLK
V
SS
SIZ(1)
SIZ(0)
ADDRESS(20)
ADDRESS(19)
ADDRESS(18)
ADDRESS(17)
ADDRESS(16)
ADDRESS(15)
ADDRESS(14)
ADDRESS(13)
ADDRESS(12)
ADDRESS(11)
V
SS(CO)
V
DD(CO)
V
DD
ADDRESS(10)
ADDRESS(9)
ADDRESS(8)
ADDRESS(7)
ADDRESS(6)
ADDRESS(5)
ADDRESS(4)
ADDRESS(3)
ADDRESS(2)
ADDRESS(1)
ADDRESS(0)
R/W
DMA_RDY
DMA_DONE
DMA_REQ
DMA_ACK
CS
RG
CS
SD
/ADDRESS(21)
162
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MPEG stream port input (bit 7); note 2
flag for bitstream error; note 2
audio data strobe for AV_DATA and A_DATA inputs; note 2
video data strobe for AV_DATA and A_DATA inputs; note 2
ground for pad ring
CPU data interface selection (0) input; note 2; note 3
27 or 40.5 MHz clock input; note 2
ground for pad ring
size of data on bus DATA (1) input; note 2
size of data on bus DATA (0) input; note 2
CPU address input (bit 20); note 2
CPU address input (bit 19); note 2
CPU address input (bit 18); note 2
CPU address input (bit 17); note 2
CPU address input (bit 16); note 2
CPU address input (bit 15); note 2
CPU address input (bit 14); note 2
CPU address input (bit 13); note 2
CPU address input (bit 12); note 2
CPU address input (bit 11); note 2
ground for core logic
supply voltage for digital core logic
supply voltage for pad ring
CPU address input (bit 10); note 2
CPU address input (bit 9); note 2
CPU address input (bit 8); note 2
CPU address input (bit 7); note 2
CPU address input (bit 6); note 2
CPU address input (bit 5); note 2
CPU address input (bit 4); note 2
CPU address input (bit 3); note 2
CPU address input (bit 2); note 2
CPU address input (bit 1); note 2
CPU address input (bit 0); note 2
read or write input; note 2
DMA ready output; note 2
DMA end input; note 2
DMA request input or output; note 2
DMA acknowledge input; note 2
chip select for control register access input; note 2
chip select for SDRAM access or CPU address (bit 21) input; note 2
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S
S
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O/Z
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I/O
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SYMBOL
PIN
TYPE
(1)
DESCRIPTION
相關PDF資料 |
PDF描述 |
|---|---|
| SAA7215 | Integrated MPEG2 AVG Decoder(綜合MPEG音頻視頻圖表譯碼器) |
| SAA7221 | Integrated MPEG2 AVG Decoder(綜合MPEG音頻視頻圖表譯碼器) |
| SAA7215HS | Integrated MPEG AVGD decoders |
| SAA7216 | Integrated MPEG2 AVG Decoder(綜合MPEG音頻視頻圖表譯碼器) |
| SAA7219HS | MPEG2 Transport RISC processor |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7221HS/C1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Integrated MPEG AVGD decoders |
| SAA7240 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:MPEG-2 Transport RISC processor |
| SAA7240HS | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:MPEG-2 Transport RISC processor |
| SAA7274 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Audio Digital Input Circuit ADIC |
| SAA7274P | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Audio Digital Input Circuit ADIC |
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