參數(shù)資料
型號(hào)： SAA7219HS
廠(chǎng)商： NXP SEMICONDUCTORS
元件分類(lèi)： 微控制器/微處理器
英文描述： MPEG2 Transport RISC processor
中文描述： 32-BIT, 81 MHz, RISC PROCESSOR, PQFP208
封裝： 28 X 28 X 3.40 MM, PLASTIC, SQFP-208
文件頁(yè)數(shù)： 11/20頁(yè)
文件大小： 84K
代理商： SAA7219HS
1
1
P
P
M
S
JTAG and Test interface (5 pins)
TDO
178
O
3-state, 2 mA output drive
3.3 V
Test data output/Target PC output.
Real-Time Trace mode off. Serial output data is
shifted from JTAG instruction register to the TDO
pin at the falling of the TCK clock. When no data is
shifted out, TDO is 3-stated.
Real-Time Trace mode on. TDO provides
non-sequential program counter output at the
processor clock speed.
Test data input/Debug interrupt.
TDI
179
I
TTL input
5 V
Real-Time Trace mode off. Serial input data (TDI) is
shifted into the JTAG instruction register or data
register on the rising edge of the TCK clock,
depending of the TAP controller state.
Real-Time Trace mode on. An active LOW level at
this input sampled by TCK positive edge, is used as
interrupt to switch the Real-Time Trace mode off
(standard JTAG).
Test mode select. This input is decoded by the TAP
controller to control test operation. Sampled on
TCK rising edge.
Test reset. Active LOW level for asynchronous reset
of the EJTAG module, independent of the processor
logic.
Test clock. Input clock used to shift data into or out
the JTAG instruction or data register.
TMS
180
I
TTL input
5 V
TRST
181
I
TTL input
5 V
TCK
184
I
TTL input
5 V
EJTAG extension reserved for PR3930 (4 pins)
DSU_CLK
185
O
2 mA output drive
3.3 V
DSU clock is equivalent to the processor clock.
Captures address and data from pin TDO when PC
trace mode is on. Is 3-stated when bit 0 or 15 of the
JTAG Control Register is logic 0.
CPU status: debug mode, pipeline stall, occurrence
of exception
PCST0 to PCST2
186, 188, 189
O
2 mA output drive
3.3 V
SYMBOL
PIN
I/O
BUFFER TYPE
VOLT
(1)
DESCRIPTION
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