
1996 Sep 27
4
Philips Semiconductors
Product specification
Digital Video Encoder (DENC)
GENLOCK-capable
SAA7199B
PINNING
SYMBOL
PIN
DESCRIPTION
V
SSD1
V
DDD1
VSN/CSYN
PD1(0)
PD1(1)
PD1(2)
PD1(3)
PD1(4)
PD1(5)
PD1(6)
PD1(7)
PD2(0)
1
2
3
4
5
6
7
8
9
10
11
12
digital ground 1 (0 V)
digital supply 1 (5 V)
vertical sync output (3-state), conditionally composite sync output; active LOW or active HIGH
data 1 input: digital signal R (red) respectively V signal; bit 0 (formats in Tables 19 to 25)
data 1 input: digital signal R (red) respectively V signal; bit 1 (formats in Tables 19 to 25)
data 1 input: digital signal R (red) respectively V signal; bit 2 (formats in Tables 19 to 25)
data 1 input: digital signal R (red) respectively V signal; bit 3 (formats in Tables 19 to 25)
data 1 input: digital signal R (red) respectively V signal; bit 4 (formats in Tables 19 to 25)
data 1 input: digital signal R (red) respectively V signal; bit 5 (formats in Tables 19 to 25)
data 1 input: digital signal R (red) respectively V signal; bit 6 (formats in Tables 19 to 25)
data 1 input: digital signal R (red) respectively V signal; bit 7 (formats in Tables 19 to 25)
data 2 input: digital signal G (green) respectively Y signal or indexed colour data; bit 0
(formats in Tables 19 to 25)
data 2 input: digital signal G (green) respectively Y signal or indexed colour data; bit 1
(formats in Tables 19 to 25)
data 2 input: digital signal G (green) respectively Y signal or indexed colour data; bit 2
(formats in Tables 19 to 25)
data 2 input: digital signal G (green) respectively Y signal or indexed colour data; bit 3
(formats in Tables 19 to 25)
data 2 input: digital signal G (green) respectively Y signal or indexed colour data; bit 4
(formats in Tables 19 to 25)
data 2 input: digital signal G (green) respectively Y signal or indexed colour data; bit 5
(formats in Tables 19 to 25)
data 2 input: digital signal G (green) respectively Y signal or indexed colour data; bit 6
(formats in Tables 19 to 25)
data 2 input: digital signal G (green) respectively Y signal or indexed colour data; bit 7
(formats in Tables 19 to 25)
load data clock input signal to input interface (samples PDn(7 to 0), CB, MPK, KEY and RTCI)
digital supply 2 (5 V)
digital ground 2 (0 V)
composite blanking input; active LOW
data 3 input: digital signal B (blue) respectively U signal; bit 0 (formats in Tables 19 to 25)
data 3 input: digital signal B (blue) respectively U signal; bit 1 (formats in Tables 19 to 25)
data 3 input: digital signal B (blue) respectively U signal; bit 2 (formats in Tables 19 to 25)
data 3 input: digital signal B (blue) respectively U signal; bit 3 (formats in Tables 19 to 25)
data 3 input: digital signal B (blue) respectively U signal; bit 4 (formats in Tables 19 to 25)
data 3 input: digital signal B (blue) respectively U signal; bit 5 (formats in Tables 19 to 25)
data 3 input: digital signal B (blue) respectively U signal; bit 6 (formats in Tables 19 to 25)
data 3 input: digital signal B (blue) respectively U signal; bit 7 (formats in Tables 19 to 25)
multi-purpose key input; active HIGH
subaddress bit A0 input for microcontroller access (Table 3)
PD2(1)
13
PD2(2)
14
PD2(3)
15
PD2(4)
16
PD2(5)
17
PD2(6)
18
PD2(7)
19
LDV
V
DDD2
V
SSD2
CB
PD3(0)
PD3(1)
PD3(2)
PD3(3)
PD3(4)
PD3(5)
PD3(6)
PD3(7)
MPK
A0
20
21
22
23
24
25
26
27
28
29
30
31
32
33