參數(shù)資料
型號(hào)： SAA7167
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： YUV-to-RGB Digital-to-Analog Converter DAC
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝： PLASTIC, SOT-313-2, LQFP-48
文件頁(yè)數(shù)： 7/20頁(yè)
文件大小： 144K
代理商： SAA7167
1995 Nov 03
7
Philips Semiconductors
Preliminary specification
YUV-to-RGB Digital-to-Analog
Converter (DAC)
SAA7167
Table 4
Pixel byte sequence of 5 : 6 : 5
For RGB 5 : 6 : 5 video inputs, the video data are just
directly bypassed to triple DACs.
The input video data can be selected to either two’s
complement (I
2
C-bus DRP-bit = 0) or binary offset
(DRP-bit = 1). The video input format is selected by
I
2
C-bus bits FMTC1 and FMTC0.
The rising edge of HREF input defines the start of active
video data. When HREF is inactive, the video output will be
blanked.
YUV-
TO
-RGB
MATRIX
The matrix converts YUV data, in accordance with
CCIR-601, to RGB data with approximately 1.5 LSB
deviation to the theoretical values for 8-bit resolution.
T
RIPLE
8-
BIT
DAC
S
Three identical DACs for R, G and B video outputs are
designed with voltage-drive architecture to provide
high-speed operation of up to 50 MHz conversion data
rate. A C
ref(h)
pin is provided to allow for one external
de-coupling capacitor to be connected between the
internal reference voltage source and ground.
INPUT
PIXEL BYTE SEQUENCE OF RGB
5 : 6 : 5
UV7
G0
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
B4
B3
B2
B1
B0
0
G0
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
B4
B3
B2
B1
B0
1
G0
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
B4
B3
B2
B1
B0
2
G0
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
B4
B3
B2
B1
B0
3
UV6
UV5
UV4
UV3
UV2
UV1
UV0
YUV7
YUV6
YUV5
YUV4
YUV3
YUV2
YUV1
YUV0
RGB data
Analog mixers and keying control
The analog mixers are controlled to switch between the
outputs from the video DACs and analog RGB inputs by a
keying signal. The analog RGB inputs need to interface
with analog mixers in the way of DC-coupling, also these
RGB inputs are limited to RGB signals without a sync level
pedestal. The keying control can be enabled by setting I
2
C
bit KEN = 1. Two kinds of keying are possible to generate:
one is external key (from EXTKEY pin when
KMOD2 to KMOD0 are logic 0), and the other is the
internal pixel colour key (when KMOD2 to KMOD0 are not
logic 0) generated by comparing the input pixel data with
the internal I
2
C-bus register value KD7 to KD0. Controlled
by KMOD2 to KMOD0 bits, there are 4 ways to compare
the pixel data (see Table 5).
Table 5
KMOD2 to KMOD0
Since only one control register KD7 to KD0 provides the
data value for pixel data comparison, when at 2
×
8-bit or
3
×
8-bit pixel input modes, it is presumed that all input
bytes (lower, middle, or higher) of each pixel must be same
as KD7 to KD0 in order to make graphics colour key
active.
The polarity of EXTKEY can be selected with KINV. With
KINV = 0, EXTKEY = HIGH switches analog mixers to
select DAC outputs. Before the internal keying signal
switches the analog multiplexers, it can be further delayed
up to 7 PCLK cycles with the control bits
KDLY2 to KDLY0.
KMOD2
to
KMOD0
PIXEL TYPE
REMARK
100
101
8-bit pixel
2
×
8-bit pixel
pseudo colour mode
high colour mode 1 with
pixels given at both rising
and falling edges of PCLK
high colour mode 2 with
pixels given only at rising
edges of PCLK
true colour mode
110
2
×
8-bit pixel
111
3
×
8-bit pixel
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